Multiprocessor Barrier Synchronization via Dedicated Registers
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Solution Overview
Problem
Existing multiprocessor systems face inefficiencies in barrier synchronization due to time-consuming memory access and arbitration requirements in both software and hardware-based methods, particularly when using shared memory or system buses.
Innovation Solution
A multiprocessor system with N processors, featuring dedicated N barrier write registers and N barrier read registers, where information is directly wired between processors, allowing for prompt reflection and understanding of synchronization states without the need for shared memory access or system bus arbitration, enabling high-speed barrier synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software synchronization using shared memory is used, then synchronization can be implemented, but access time increases and processing speed decreases
Solution Approach 1:
The patent extracts the synchronization state information from shared memory and places it in dedicated barrier read registers (112) within each processor. This extraction eliminates the need for processors to access shared memory for synchronization status, thereby reducing memory access time and improving processing speed while maintaining synchronization capability.
Solution Approach 2:
The patent introduces barrier read registers (112) and barrier write registers (111) as intermediary components between processors. These registers act as mediators that hold synchronization state information locally, allowing processors to check synchronization status without directly accessing shared memory, thus reducing access time while preserving synchronization reliability.
2Speed
If hardware-based synchronization with system bus is used, then synchronization speed improves, but bus arbitration requirements increase complexity
Solution Approach 1:
The patent extracts the synchronization state information from the system bus and places it in local barrier read registers (112) within each processor. This extraction eliminates the need for continuous bus arbitration to check synchronization status, reducing system bus traffic and arbitration complexity while maintaining high synchronization speed through direct register access.
Solution Approach 2:
The patent introduces barrier read registers (112) and barrier write registers (111) as intermediary components that cache synchronization state information. These registers mediate between the system bus and processors, allowing processors to obtain synchronization status locally without requiring bus arbitration, thus reducing complexity while preserving speed.
3Productivity
If dedicated barrier registers with direct wiring are used, then synchronization processing speed increases, but hardware cost increases
Solution Approach 1:
The patent makes the barrier read registers (112) and barrier write registers (111) universal components that are integrated into each processor's control unit. These registers serve multiple functions: storing synchronization state, enabling local status checking, and facilitating high-speed synchronization without requiring separate dedicated hardware for each processor pair, thus improving productivity while controlling hardware complexity.
Solution Approach 2:
The patent merges the barrier read registers (112) and barrier write registers (111) into the control unit (103) of each processor. This integration combines multiple synchronization functions into a unified hardware structure, reducing the need for separate dedicated components between processor pairs and achieving high synchronization speed while managing hardware complexity through consolidation.
Data Source
AI summary
Each of processors has a barrier write register and a barrier read register. Each barrier write register is wired to each barrier read register by a dedicated wiring block. For example, a 1-bit barrier write register of a processor is connected, via the wiring block, to a first bit of each 8-bit barrier read register contained in the processors, and a 1-bit barrier write register of another processor is connected, via a wiring block, to a second bit of each 8-bit barrier read register contained in the processors. For example, a processor writes information to its own barrier write register, thereby notifying synchronization stand-by to the other processors and reads its own barrier read register, thereby recognizing whether the other processors are in synchronization stand-by or not. Therefore, a special dedicated instruction is not required along barrier synchronization processing, and the processing can be made at a high speed.