Multiprocessor Cache Coherence via Data Switching and Directory Nodes

The patent segments the cache coherence management by dividing processor nodes into different groups (first group and second group) with separate interconnect paths. When a processor node needs to access data, it only communicates with nodes in its own group rather than broadcasting to all nodes system-wide. This segmentation reduces communication delay while maintaining cache coherence within each group.

The patent introduces directory nodes as intermediaries that manage cache coherence information for groups of processor nodes. Instead of direct processor-to-processor communication or system-wide broadcasting, the directory node acts as a mediator that receives access requests, determines the appropriate cache node, and forwards requests selectively. This intermediary approach reduces unnecessary communications and power consumption.

The patent divides the processor network into multiple groups with separate interconnect paths, so that cache coherence messages are confined to local groups rather than being broadcast system-wide. This segmentation significantly reduces the number of nodes that need to process coherence messages, thereby reducing overall power consumption while maintaining data consistency within each group.

Instead of performing system-wide broadcasting for every cache access, the patent applies partial action by only initiating coherence protocols within the necessary subset of processor nodes (those in the same group). This selective approach reduces power consumption by avoiding unnecessary message transmission and processing in nodes that do not need the data.

The patent segments the interconnect structure into multiple independent paths connecting different processor node groups to memory devices. This allows multiple groups to access memory simultaneously through different paths, eliminating the sequential bottleneck of a single shared bus. The system can be extended by adding more groups and paths without disrupting existing operations, improving both performance and extensibility.

The patent transitions from a one-dimensional sequential bus architecture to a multi-dimensional interconnect structure where processor groups are organized in a hierarchical manner with multiple access paths. This dimensional change allows parallel access operations and provides scalability by enabling the addition of new groups along different dimensions of the interconnect network.