Multiprocessor Cache Coherency Latency Reduction via Direct Data Path
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Solution Overview
Problem
In distributed shared memory multiprocessor systems, ensuring data coherency among multiple cells while maintaining processing speed is challenging due to latency issues arising from different paths for reply and request write backs, which can lead to data inconsistency.
Innovation Solution
Implementing a configuration where the owner cell directly transmits data to the request cell during a read request, and the request cell performs a request write back with directory update information to ensure coherency, while aborting the reply write back if it arrives after the request write back, thus maintaining coherency and reducing latency to 3HOP.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the owner cell transmits reply data directly to the request cell, then processing speed is improved, but data coherency cannot be ensured due to different paths for reply write back and request write back
Solution Approach 1:
The home cell acts as an intermediary to coordinate between the owner cell and request cell. It receives the reply write back from the owner cell, updates the directory, and manages the timing to ensure coherency is maintained while enabling direct data transmission for speed improvement.
Solution Approach 2:
The home cell performs preliminary actions by updating the directory and preparing the system state before the request write back arrives. This allows the system to quickly handle the request write back without waiting for directory updates, improving processing speed while maintaining coherency.
2Reliability
If the reply write back is aborted when request write back arrives first, then data coherency is maintained, but additional control complexity is introduced
Solution Approach 1:
The home cell uses feedback from the request write back to determine whether to abort the reply write back. When the request write back arrives first, it provides feedback that the directory should be updated, triggering the home cell to abort the incoming reply write back and maintain coherency.
Solution Approach 2:
The system dynamically adjusts the handling of reply write back based on the timing of request write back arrival. The home cell can either accept or abort the reply write back depending on the current system state, providing flexible control that balances coherency requirements with processing efficiency.
Data Source
AI summary
The multiprocessor system includes multiple cells having identical functions, and each of the multiple cells has a processor, a cache memory, and a main memory. The multiple cells include the first cell as a request cell, the second cell as a home cell, and the third cell as an owner cell. The latest version of the target data stored in the main memory of the second cell is stored in the cache memory of the third cell. When the first cell issues a read request for the target data to the second cell, the second cell issues a snoop request to the third cell in response to the read request. The third cell directly transmits the target data to the first cell in response to the snoop request. Also, the third cell issues the reply write back to the second cell in response to the snoop request. The first cell issues a request write back to the same address as that of the target data in the second cell. The second cell discards the reply write back when the reply write back from the third cell is received later than the request write back from the first cell.