Multiprocessor System Cache Architecture with Segmented Coherence
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Solution Overview
Problem
In multiprocessor architectures, maintaining cache coherence across multiple CPUs or CPU chiplets is crucial for achieving high-performance scaling, but existing technologies face challenges in efficiently managing concurrent read and write requests, leading to increased latencies.
Innovation Solution
A system cache architecture that includes a snooping pipeline switch, multiple cache segments, a memory request arbiter, and a coherent interconnect snooping requester, which reduces data request interactions between the coherent interconnect and processors, and supports high-performance scaling by effectively handling concurrent requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a coherent interconnect is used to maintain cache coherence across multiple CPUs or CPU chiplets, then cache coherence is maintained, but data request interactions increase leading to increased latencies
Solution Approach 1:
The system cache is divided into multiple cache segments (first cache segment, second cache segment, etc.), each capable of independently handling data requests. This segmentation allows concurrent processing of multiple requests across different segments, reducing the latency caused by sequential processing in a single cache while maintaining cache coherence through the snooping pipeline switch.
2Productivity
If multiple cache segments are introduced to handle concurrent requests, then request processing capability is improved, but system complexity increases
Solution Approach 1:
Each cache segment is designed with universal functionality to handle both processor data requests and DMA master snooping requests. The snooping pipeline switch provides a unified interface that routes different types of requests to appropriate cache segments, allowing the system to process multiple concurrent requests without requiring separate dedicated structures for each request type, thereby managing complexity while improving productivity.
Data Source
AI summary
A system cache architecture for supporting a multiprocessor architecture includes: a snooping pipeline switch, at least two cache segments, a memory request arbiter and a coherent interconnect snooping requester. The snooping pipeline switch is connected to a last level memory bus of at least two processors of the multiprocessor architecture, and forwards a memory read or write request from any processor to a memory system by means of the memory request arbiter or sends the memory read or write request to any one of the at least two cache segments; the coherent interconnect snooping requester sends a snooping read or write request from a DMA master to any two cache segment; the at least two cache segments are configured to in response to concurrent read or write requests from the snooping pipeline switch or from the coherent interconnect snooping requester, feed back or update stored cached data.