Multi-Processor Clock Architecture with Local Oscillators

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Solution Overview

Problem

Centralized global clock architectures in multi-processor systems are prone to catastrophic failures, affecting the entire system if the clock fails, leading to a single point of failure (SPOF) and potential system downtime.

Innovation Solution

Implementing a clock architecture with local clock sources on individual modules, using dedicated oscillators to generate reference clock signals, and incorporating multiplexers to switch between global and local clock signals based on operating system capabilities, allowing for independent clock management within partitions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a centralized global clock architecture is used to supply clock signals to all processors, then clock signal distribution is simplified and synchronized, but the system becomes vulnerable to single point of failure where a clock failure causes catastrophic system-wide failure

Engineering Contradiction:
Improveclock signal distribution architectureVSAvoidsystem reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent divides the centralized clock system into multiple independent local clock sources, one for each cell or partition. Each local clock source operates independently, so a failure in one cell's clock does not affect other cells. This segmentation transforms the single point of failure into multiple distributed points, significantly improving system reliability while maintaining manageable complexity through modular architecture.

Inventive Principle:
Principle #1Segmentation

2Reliability

If local clock sources are implemented in each cell to improve reliability and enable partition-level recovery, then system reliability increases and partition-level operation is enabled, but device complexity and the number of clock sources increase

Engineering Contradiction:
Improvesystem reliabilityVSAvoidclock architecture complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements local clock sources specifically at the cell level, giving each cell its own independent clock generation capability. This local quality enhancement allows each partition to operate autonomously with its own timing, enabling partition-level recovery while containing the complexity increase to only what is necessary for local autonomy rather than system-wide complexity.

Inventive Principle:
Principle #3Local quality

3Adaptability or versatility

If multiplexers are used to switch between global and local clock signals based on operating system capabilities, then adaptability to diverse operating systems is improved, but device complexity increases

Engineering Contradiction:
Improveoperating system compatibilityVSAvoidclock switching mechanism
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces dynamic switching capability through multiplexers that can adaptively select between global and local clock sources based on operating system requirements. This dynamic configuration allows the system to optimize clock distribution for different OS types (e.g., real-time vs. general-purpose) while containing complexity through standardized switching mechanisms that can be controlled via software configuration rather than hardware redesign.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7814301B2Clock architecture for multi-processor systems
Publication Date: 2010.10.12 HEWLETT PACKARD ENTERPRISE DEV LP
  • US7814301B2 patent drawing
  • US7814301B2 patent drawing
  • US7814301B2 patent drawing

AI summary

In one embodiment, a computer system, comprises at least a first computing cell and a second computing cell, each computing cell comprising at least one processor, a routing device to couple the first and second computing cells, a global clock signal source coupled to the at least two computing cells to generate a global clock signal, at least one timing manager to generate a timing control signal, wherein the at least two computing cells comprise a local oscillator to generate a local clock signal, and a multiplexer coupled to receive the global clock signal, the local clock signal, and the timing control signal, and to output one of the global clock signal or the local clock signal in response to the control signal.