Multiprocessor Data Exchange via Segmented Routing and Buffers

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Solution Overview

Problem

Conventional data exchange mechanisms in multiprocessor systems are limited by serialization, resource-intensive connections, and scalability issues, which hinder parallel execution and efficiency in embedded applications.

Innovation Solution

A system and method utilizing data exchange buffers and routing modules that allow flexible data exchange between processing modules, enabling simultaneous data transfer and routing through predetermined paths, with modes like ping-pong and FIFO, and a rotating priority scheme for efficient channel allocation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a common bus with arbitrator is used for data exchange, then any processor can communicate with any other processor, but communication gets serialized and processing is delayed

Engineering Contradiction:
Improvecommunication flexibilityVSAvoidprocessing speed
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent segments the communication system into multiple independent point-to-point links between processors, replacing the single common bus. Each link operates independently, allowing simultaneous data transfers between different processor pairs, thus eliminating serialization while maintaining communication flexibility.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces dedicated link controllers as intermediary devices that manage individual point-to-point connections. These controllers handle protocol management, flow control, and arbitration locally, enabling parallel communication without requiring a centralized bus arbitrator that serializes all traffic.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If dedicated links connect every processor directly to every other processor, then parallel execution is achieved, but resource consumption increases

Engineering Contradiction:
Improveparallel execution capabilityVSAvoidconnection resources
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements local quality by providing direct dedicated links only for communication paths that are most frequently used or critical for parallel execution. Not all processor pairs have direct links; instead, the system provides high-speed direct connections for essential communication patterns while accepting indirect paths for less critical traffic, thus reducing overall resource consumption while maintaining parallel execution capability.

Inventive Principle:
Principle #3Local quality

3Productivity

If shared memory is used for data exchange, then source processor can proceed to next job, but synchronization is required and parallel communication is limited by memory ports

Engineering Contradiction:
Improveprocessor throughputVSAvoidsynchronization overhead
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces message buffers as intermediary storage devices located at each communication endpoint. These buffers decouple the producer and consumer processors, allowing the source processor to write data and proceed to the next job without waiting for the destination processor. The buffers automatically manage data availability and eliminate the need for complex synchronization protocols, while enabling parallel communication beyond memory port limitations.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8032654B2System and method for data exchange in multiprocessor computer systems
Publication Date: 2011.10.04 INFOSYS LTD
  • US8032654B2 patent drawing
  • US8032654B2 patent drawing
  • US8032654B2 patent drawing

AI summary

A system for data exchange in multiprocessor computer system is disclosed. The system includes at least one processing module adapted to communicate with at least one of a plurality of routing modules or a plurality of buffer modules or both and at least one communicating interfaces to facilitate data exchange in multiprocessor computer system.