Multiprocessor Execution Control Circuit Speed and Complexity
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Solution Overview
Problem
Multiprocessor systems face challenges in achieving speed-up without compromising flexibility and expandability, particularly in execution control processing, due to centralized processing loads and complex circuit configurations that are inflexible and difficult to expand.
Innovation Solution
A multiprocessor system with an execution control circuit that includes an execution control processor, a control bus output unit, a status bus input unit, a determination circuit to assess dependency between status notifications and processing commands, a status accelerator for high-speed processing, and a status FIFO control unit to process notifications using the execution control processor, allowing for flexible and efficient execution control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a dedicated execution control circuit is used to decentralize processing loads and speed up operation, then processing speed improves, but circuit configuration becomes complex and expandability decreases
Solution Approach 1:
The execution control circuit is divided into multiple independent execution control units, each capable of handling specific sub-processors. This segmentation allows parallel processing operations while keeping each unit's configuration manageable and independent, thus improving processing speed without proportionally increasing overall system complexity
Solution Approach 2:
The execution control circuit employs a dynamic configuration where the number and arrangement of execution control units can be adjusted based on system requirements. This dynamic approach allows the circuit to adapt to different processing needs while maintaining a relatively simple base configuration, resolving the contradiction between speed and complexity
2Productivity
If the number of sub-processors is increased to improve processing capacity, then productivity improves, but the circuit configuration of the execution control unit must be changed, reducing expandability
Solution Approach 1:
Each execution control unit is designed with universal functionality to handle multiple types of sub-processors and processing tasks. This multi-functionality allows the same circuit configuration to work with different numbers and types of sub-processors, improving processing capacity while maintaining expandability without requiring configuration changes
Solution Approach 2:
The execution control units are designed in a nested or modular structure where additional units can be added to the system without reconfiguring existing units. This nested approach allows incremental expansion of processing capacity while preserving the original configuration, thus maintaining expandability
3Adaptability or versatility
If software processing is used on the execution control processor to improve flexibility, then adaptability improves, but processing time increases to several tens to hundreds of cycles
Solution Approach 1:
The system merges hardware execution control units with software-based execution control processors, creating a hybrid architecture. The hardware units handle time-critical operations immediately, while the software processor manages complex control logic and coordination, thus achieving both speed and flexibility simultaneously
Data Source
AI summary
The multiprocessor system includes one or a plurality of main processors and a plurality of sub-processors, and an execution control circuit which conducts execution control of each the sub-processors, wherein the execution control circuit includes an execution control processor for execution control processing of each the sub-processors, a control bus output unit for activation of a command to each the sub-processors, a status bus input unit for status notification from each the sub-processors, a determination circuit which determines whether or not the status notification has one-to-one dependency with a processing command to be issued next on an operation sequence and is to be processed at a high speed, a status accelerator which issues a corresponding processing activation command when the status notification is to be processed at a high speed, and a status FIFO control unit which processes the status notification by using the execution control processor.