Multiprocessor System Independent Flash Memory Access
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Solution Overview
Problem
Current data processing systems face limitations in handling large volumes of data due to constraints in memory access and parallel processing, leading to inefficiencies in data management and performance, especially when dealing with applications requiring extensive memory operations.
Innovation Solution
A multiprocessor system with direct access to bulk solid-state memory resources, utilizing a multi-rooted architecture that connects multiple central processing units (CPUs) to flash memory, enabling efficient parallel access and management of data through specialized software and hardware components, including memory controllers, flash interfaces, and data protection mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple CPUs share a single memory interface, then device complexity is reduced, but memory access speed and parallel processing capability deteriorate
Solution Approach 1:
The patent divides the single memory interface into multiple independent interfaces, with each CPU having its own dedicated memory interface and path to flash memory resources. This segmentation eliminates the bottleneck of shared interfaces while maintaining manageable system complexity through modular architecture.
Solution Approach 2:
The patent introduces multiple dimensions of parallelism by creating independent memory access paths for each CPU, allowing simultaneous memory operations across different CPUs without interfering with each other, thereby dramatically improving memory access speed and parallel processing capability.
2Device complexity
If a single CPU accesses memory sequentially, then device complexity is simplified, but productivity and data processing efficiency deteriorate
Solution Approach 1:
The patent segments the memory access architecture into multiple independent CPU paths, allowing parallel data processing operations. Each CPU can independently access and process different portions of data simultaneously, dramatically improving productivity for large-scale data processing applications.
Solution Approach 2:
The patent enables continuous parallel memory access operations across multiple CPUs, eliminating idle time and ensuring that all processing units are continuously utilized for productive work, thereby maximizing data processing efficiency.
3Device complexity
If memory resources are centralized, then device complexity is reduced, but adaptability and scalability for large data volumes deteriorate
Solution Approach 1:
The patent segments memory resources into multiple independently accessible flash memory units, each reachable through dedicated CPU interfaces. This segmentation allows the system to scale to large data volumes by adding more memory units and CPUs while maintaining manageable complexity through standardized interface modules.
Solution Approach 2:
The patent creates a universal memory access architecture where each CPU interface can access any flash memory resource through standardized protocols and address mapping mechanisms, providing both simplicity in management and high adaptability for handling diverse and large-scale data processing requirements.
Data Source
AI summary
A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.