Multiprocessor Power Control via Instruction Conversion
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Solution Overview
Problem
In multiprocessor systems, especially in mobile-embedded computing, there is a challenge in reducing electric power consumption when temporarily activating high-power processors, as existing methods either increase overhead or fail to achieve expected power savings due to the need for frequent activation and deactivation of processors.
Innovation Solution
A multiprocessor control apparatus and method that includes a low-power consumption processor and a high-performance processor, with an instruction converting section that converts the high-performance processor's instruction code into a format executable by the low-power processor, allowing the low-power processor to execute the code when the high-performance processor is suppressed, thereby reducing the need for its activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high-performance processor is used to execute programs, then processing speed and performance are improved, but electric power consumption increases
Solution Approach 1:
The system dynamically switches between high-performance processor and low-power processor based on operational requirements. The control section activates the appropriate processor type depending on whether high-speed processing is needed or power saving is prioritized, making the processor selection adaptive rather than static
Solution Approach 2:
The system changes the operational parameters by switching between different processor types with different power consumption characteristics. When power saving is required, the system transitions from using the high-performance processor to using the low-power processor, effectively changing the power consumption parameter while maintaining operational capability
2Reliability
If the high-performance processor is temporarily activated during power-saving operations, then necessary processing can be performed, but electric power consumption increases and activation/deactivation overhead occurs
Solution Approach 1:
The system performs preliminary action by pre-converting instruction codes from the high-performance processor format to the low-power processor format and storing them in memory. This preparation work is done in advance so that when power-saving mode is activated, the low-power processor can immediately execute the pre-converted instructions without needing to activate the high-performance processor
Solution Approach 2:
The system creates a copy of the instruction code in a different format. The instruction converting section converts the original high-performance processor instruction codes into low-power processor instruction codes and stores these copies in memory. The low-power processor then executes these copied instructions, eliminating the need to activate the high-performance processor
3Adaptability or versatility
If instruction code conversion is performed, then the low-power processor can execute high-performance processor code, but conversion overhead and processing time are added
Solution Approach 1:
The instruction converting section performs the conversion work in advance by converting high-performance processor instruction codes to low-power processor instruction codes before execution is needed. The converted codes are stored in memory for later use, so when power-saving mode is activated, no real-time conversion is needed and the low-power processor can immediately execute the pre-converted instructions
Data Source
AI summary
An object of the invention is to reduce the electric power consumption resulting from temporarily activating a processor requiring a large electric power consumption, out of a plurality of processors. A multiprocessor system (1) includes: a first processor (141) which executes a first instruction code; a second processor (151) which executes a second instruction code, a hypervisor (130) which converts the second instruction code into an instruction code executable by the first processor (141); and a power control circuit (170) which controls the operation of at least one of the first processor (141) and the second processor (151). When the operation of the second processor (151) is suppressed by the power control circuit (170), the hypervisor (130) converts the second instruction code into the instruction code executable by the first processor (141), and the first processor (141) executes the converted instruction code.