Multi-processor circuit with differentiated memory bank access
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Solution Overview
Problem
Multi-processor systems face memory access conflicts and inefficiencies in memory utilization, leading to degraded worst-case performance, especially when handling real-time tasks and maintaining consistency across cache memories.
Innovation Solution
A multi-processor circuit design with parallel access to shared memory banks, utilizing a differentiated conflict resolution scheme and a defragmenter to prioritize access frequencies and remap addresses, allowing processors to efficiently use memory banks while maintaining real-time performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a shared memory is used for all processors, then memory utilization efficiency is improved, but system performance deteriorates due to access conflicts
Solution Approach 1:
The memory system is segmented into multiple memory banks, each accessible by multiple processors. This segmentation allows parallel access to different memory banks, reducing conflicts while maintaining high utilization. The arbitration logic further segments access rights by assigning higher priority to local memory banks for each processor.
Solution Approach 2:
Each processor is assigned a local memory bank with higher access priority, creating local quality differences in access rights. This ensures that processors can efficiently access their local memory while still sharing other memory banks when needed, balancing performance and utilization.
2Object-affected harmful factors
If cache memories are provided between processors and main memory, then access conflicts are reduced, but worst-case performance deteriorates due to long response times
Solution Approach 1:
The patent extracts the conflict resolution function from the memory access path by implementing arbitration logic that proactively manages access rights before conflicts occur. This eliminates the need for cache memories while preventing access conflicts through priority-based arbitration.
Solution Approach 2:
The arbitration logic performs preliminary action by pre-establishing access priorities and detecting potential conflicts before they occur. This allows the system to prevent conflicts proactively rather than handling them reactively through cache mechanisms, maintaining deterministic response times.
3Object-affected harmful factors
If cache memories are used to mitigate access conflicts, then system complexity increases due to consistency maintenance requirements
Solution Approach 1:
The patent removes cache memories from the architecture entirely, extracting the conflict mitigation function and implementing it through arbitration logic instead. This eliminates the complexity of maintaining consistency across multiple cache memories while still resolving access conflicts effectively.
4Object-affected harmful factors
If each processor is provided with its own memory bank, then access conflicts are eliminated, but memory efficiency deteriorates due to dimensioning for most demanding tasks
Solution Approach 1:
Multiple memory banks are merged into a shared memory system that is accessible by multiple processors. This combining allows memory to be efficiently utilized across different processors while the arbitration logic ensures that access conflicts are resolved in favor of local memory banks when needed.
Solution Approach 2:
The system implements local quality by giving each processor preferential access rights to its local memory bank through priority arbitration. This allows memory banks to serve dual purposes: as dedicated local memory when needed and as shared memory when not in use, improving overall efficiency.
Data Source
AI summary
A plurality of processors in a multiprocessor circuit is electrically connected to a plurality of independently addressable memory banks via a connection circuit. The connection circuit is arranged to forward addresses from a combination of the processors to addressing inputs of memory banks selected by the addresses. The connection circuit provides for a conflict resolution scheme wherein at least one of the processors is associated with one of the memory banks as an associated processor. The connection circuit guarantees the associated processor a higher minimum guaranteed access frequency to the associated memory banks than to non-associated memory banks. A defragmenter detects data associated with a task running on the associated processor that is stored on one of the memory banks and moves the data to the associated memory banks during execution of the task.