Multiprocessor Memory Access via Bus Bridges
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Solution Overview
Problem
In multiprocessor architectures, accessing shared resources such as shared memory and local memories simultaneously at high speeds is challenging due to the low speed of system buses and the inefficiency of existing methods like spin lock for exclusive access, which hinder parallel processing and increase execution time.
Innovation Solution
A data processing system design that includes multiple processors, local memories, and bus bridges connected via high-speed local and system buses, allowing for simultaneous high-speed access to local and shared memories through request signals and acknowledge signals, enabling exclusive access and reducing bus traffic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spin lock method is used for exclusive access to shared memory, then access control is achieved, but execution time increases and processing efficiency decreases
Solution Approach 1:
The patent extracts the lock variable from shared memory and places it in local memory, separating the locking mechanism from the shared resource. This allows processors to check and set lock variables in local memory without accessing shared memory, eliminating the time-consuming shared memory access while maintaining exclusive access control through the bus bridge interface.
Solution Approach 2:
The bus bridge acts as an intermediary between local memory and shared memory. It monitors access requests to lock variables in local memory and grants or denies access to shared memory accordingly, enabling efficient lock management without requiring direct shared memory access for every lock operation.
2Adaptability or versatility
If system bus is used for memory access, then connectivity between processors and memories is achieved, but access speed is limited
Solution Approach 1:
The patent segments the memory system into local memory (coupled to each processor via high-speed local bus) and shared memory (coupled via system bus). This segmentation allows frequent operations to occur on the fast local bus while the slower system bus is used only when shared memory access is required, optimizing overall system performance.
Solution Approach 2:
Each processor is equipped with its own local memory and high-speed local bus, providing fast access paths for processor-specific operations. The local memory serves as a high-speed cache or buffer, while shared memory provides slower but shared access, creating different access qualities for different memory types.
3Productivity
If multiple processors access shared memory simultaneously, then parallel processing is enabled, but bus contention occurs and access efficiency decreases
Solution Approach 1:
Processors perform preliminary actions by checking and setting lock variables in their own local memory before attempting to access shared memory. This preliminary locking mechanism in local memory allows processors to prepare for shared memory access without causing bus contention, as the lock variable access occurs on the fast local bus rather than the shared system bus.
Data Source
AI summary
In a multiprocessor, one of two local memories can be accessed at a high speed by one of the two processors and also accessed by the other processor. In a multiprocessor, first and second local memories are coupled to first and second processors via first and second local buses. First and second bus bridges are coupled to a system bus and the first and second local buses. First and second bus interface units are coupled to the system bus and the first and second local memories. A high-speed access is made from the first processor to the first local memory via the first local bus. The first local memory is also accessed from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit and from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit. A high-speed access is made from the second processor to the second local memory via the second local bus. The second local memory is also accessed from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit and from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit.