Point-to-Point Multiprocessor Power Management
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Solution Overview
Problem
Modern multiprocessor systems face challenges in reducing power consumption and heat generation, as existing low-power states often compromise performance, and completely powering down processors can cause impedance mismatches on shared buses, leading to inefficiencies and potential system crashes.
Innovation Solution
Implementing a point-to-point multiprocessor system where each processor pair has its own communication bus, allowing for complete power removal from individual processors, including cores and I/O ports, without causing impedance mismatches, and using control logic to manage power distribution based on workload demands through scheduling, monitoring, and hybrid approaches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If processors are completely powered down to reduce power consumption and heat generation, then power savings increase, but impedance mismatches occur on shared buses causing system instability
Solution Approach 1:
The patent segments the processor system into individual point-to-point communication channels, allowing each processor to be independently powered down without affecting the impedance of the entire bus. This segmentation enables selective power management where idle processors can be completely shut off while active processors maintain stable communication channels.
Solution Approach 2:
The patent extracts processors from the shared bus architecture, removing them from the electrical bus environment when they are not in use. By taking processors out of the bus system through complete power down, the impedance mismatch problem is eliminated since the processor is no longer electrically connected to the bus.
2Reliability
If processors remain powered on to maintain impedance matching, then system reliability is maintained, but power consumption and heat generation increase
Solution Approach 1:
By dividing the communication system into dedicated point-to-point links rather than a shared bus, each active processor maintains impedance matching on its own channel without needing to keep inactive processors powered on. This segmentation allows the system to maintain reliability on active channels while powering down inactive ones.
3Device complexity
If a shared bus architecture is used for processor communication, then device complexity is reduced, but power consumption increases due to inability to fully power down processors
Solution Approach 1:
The patent replaces the shared bus architecture with segmented point-to-point communication channels. While this increases structural complexity, it enables complete power down of inactive processors since each processor has its own dedicated channel that maintains impedance characteristics independently of other processors.
Solution Approach 2:
The patent transitions from a one-dimensional shared bus where all processors share the same electrical medium to a multi-dimensional architecture where each processor pair has its own communication dimension. This allows independent power management of each processor without affecting the electrical characteristics of the communication medium.
Data Source
AI summary
The present invention provides a multiprocessor system and method in which power can be withheld from a core and inter-processor communications ports of a first processor while power continues to be supplied to a second processor.