Multiprocessor Secondary Network With Bidirectional Low-Latency Channels
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Solution Overview
Problem
Existing multiprocessor systems lack an efficient secondary interconnection network that supports urgent communications with low latency and guaranteed message delivery, while also facilitating debug and system administration functions.
Innovation Solution
A multiprocessor system with a primary interconnection network and an improved secondary interconnection network (SIN) that includes a daisy-chain architecture of interface units, a bus controller for arbitration, and a processor interface block for full duplex communication, allowing processors to access the SIN through the primary network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a serial bus architecture is used for the secondary interconnection network, then guaranteed message delivery and minimum area are achieved, but latency increases and bandwidth is reduced
Solution Approach 1:
The secondary interconnection network is segmented into multiple independent bidirectional channels instead of a single serial bus. Each channel can operate simultaneously, allowing parallel message transmission. This segmentation enables guaranteed delivery through dedicated channels while reducing latency by eliminating the sequential bottleneck of a single serial bus.
Solution Approach 2:
The patent transitions from a one-dimensional serial bus architecture to a multi-dimensional channel-based architecture. Multiple bidirectional channels provide parallel communication paths, adding a temporal and spatial dimension to message transmission. This dimensional expansion allows simultaneous messages to be sent across different channels, reducing overall latency while maintaining reliability through dedicated pathways.
2Area of stationary object
If a serial bus architecture is used for the secondary interconnection network, then minimum area and power dissipation are achieved, but bandwidth is reduced
Solution Approach 1:
The communication capacity is segmented into multiple independent channels instead of relying on a single wide serial bus. Each channel uses simpler, narrower interconnects that consume less area, while the collective bandwidth of multiple channels provides the necessary throughput. This segmentation achieves both low area consumption and adequate bandwidth by distributing communication across parallel simple channels.
Solution Approach 2:
The patent adds multiple parallel dimensions to the communication architecture. Instead of using a single wide bus, it employs multiple narrower channels operating simultaneously. This multi-dimensional approach increases total bandwidth through parallelism while keeping individual channel area minimal, effectively decoupling bandwidth requirements from area consumption.
3Quantity of substance
If a primary interconnection network is optimized for high bandwidth, then throughput is improved, but latency increases
Solution Approach 1:
The communication needs are segmented into two separate networks: a primary network for high-bandwidth throughput-oriented messages and a secondary network for low-latency critical messages. This segmentation allows each network to be optimized for its specific function without compromise. The secondary network's guaranteed delivery mechanism ensures low latency for critical communications while the primary network handles bulk data transfer with high throughput.
Solution Approach 2:
Different quality characteristics are assigned to different communication pathways based on local needs. The secondary interconnection network provides guaranteed delivery and low latency for critical messages, while the primary network provides high bandwidth for throughput-intensive operations. Each network is locally optimized for its specific performance requirements rather than attempting to satisfy all requirements uniformly.
Data Source
AI summary
Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.