Multiprocessor System Management Interrupt Handling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multiprocessor systems, software-based system management interrupts can be superseded by subsequent hardware-based interrupts, leading to potential handling issues and operational disruptions.
Innovation Solution
A system and method where a primary processor recognizes system management interrupts, writes a reason code, and sets a watchdog timer to ensure all processors enter system management mode, allowing software-based interrupts to be handled without being superseded by hardware-based ones, and signals other processors to exit this mode after handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all processors are required to generate a system management interrupt when one processor generates it, then system management mode is ensured across all processors, but the risk increases that software-based interrupts may be superseded by subsequent hardware-based interrupts
Solution Approach 1:
The patent applies preliminary action by having the primary processor write a reason code to a storage location and set a watchdog timer before all processors enter system management mode. This preliminary setup ensures that when processors later handle interrupts, they can check the reason code to determine if it's a software-based interrupt that should not be superseded, thus preventing loss of interrupt handling integrity while maintaining system management mode consistency
Solution Approach 2:
The patent uses the reason code stored in a storage location as an intermediary mechanism. This reason code acts as a mediator between the primary processor's interrupt generation and the other processors' interrupt handling, providing information that prevents software-based interrupts from being incorrectly superseded by hardware-based interrupts, thereby resolving the contradiction between reliability and information loss
2Reliability
If a watchdog timer is set to expire and cause all processors to enter system management mode, then interrupt handling is synchronized across processors, but system complexity increases
Solution Approach 1:
The watchdog timer is designed to serve multiple functions: it not only triggers system management mode entry for all processors but also serves as a synchronization mechanism for interrupt handling. By making the watchdog timer multi-functional, the patent reduces overall system complexity while maintaining reliable interrupt synchronization across all processors
3Reliability
If the primary processor writes a reason code and sets a watchdog timer, then software-based interrupts can be identified and protected from supersession, but the processing overhead increases
Solution Approach 1:
The patent extracts the interrupt protection logic into a separate, dedicated mechanism using the reason code in the storage location. By taking out the protection function as a distinct element, processors can quickly check the reason code without complex processing, thus protecting software-based interrupts from supersession while minimizing processing overhead and time loss
Data Source
AI summary
A system and method is disclosed for managing system management interrupts in a multiprocessor system. The system described herein includes multiple processors, each of which may be directly coupled to memory. A primary processor will recognize the initiation of a system management interrupt. The primary processor will write a reason code to a storage location and set a watchdog timer, the expiration of which causes all of the processors of the system to enter a system management mode. After all of the processors have entered system management mode, it is determined if the reason code of the storage location corresponds to certain software-based system management interrupts. If so, the system management interrupt is handled by the local processors. Following the handling of the system management interrupt by the local processor, a signal is sent to each of the other processors to cause the processors to exit system management mode.