Multiprocessor Task Scheduler Conflict Detection

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Solution Overview

Problem

Conventional multiprocessor systems face task failures due to conflicts between processors accessing shared resources, which hinder real-time performance guarantees.

Innovation Solution

A multiprocessor system with a scheduler management device that detects potential task failures by analyzing access conflicts and adjusts task execution orders to prevent failures, using a command unit to change task schedules based on stored failure patterns and periodic scheduling information.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple processors execute tasks simultaneously to improve productivity, then processing throughput increases, but access conflicts to shared resources occur causing task failures

Engineering Contradiction:

Improveprocessing throughputVSAvoidtask completion reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The failure pattern storage unit stores failure patterns in advance based on historical task execution information. The task comparison unit compares scheduled task execution orders against these pre-stored failure patterns before execution occurs, enabling preventive detection and avoidance of access conflicts that would cause task failures.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system collects task execution information from multiple processors, analyzes it to identify failure patterns, and feeds this information back to the scheduling mechanism. This feedback loop enables the system to learn from past conflicts and adjust future scheduling decisions to avoid recurring issues.

Inventive Principle:

Principle #23Feedback

2Device complexity

If task execution order is fixed to simplify scheduling, then scheduling complexity reduces, but access conflicts cannot be avoided leading to real-time performance degradation

Engineering Contradiction:

Improvescheduling complexityVSAvoidreal-time performance guarantee

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The system automatically detects potential failures by comparing scheduled tasks against stored failure patterns and autonomously determines whether to reject or modify the schedule. This self-service mechanism eliminates the need for complex manual scheduling analysis while ensuring real-time performance guarantees through automated conflict detection.

Inventive Principle:

Principle #25Self-service

3Reliability

If dynamic task scheduling is implemented to avoid access conflicts, then task completion reliability improves, but scheduling complexity increases

Engineering Contradiction:

Improvetask completion reliabilityVSAvoidscheduling complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Instead of implementing complex real-time analysis of all possible task conflicts, the system creates simplified copies of failure scenarios in the failure pattern storage unit. The task comparison unit then performs simple pattern matching against these copies, achieving high reliability through lightweight comparison operations rather than complex scheduling algorithms.

Inventive Principle:

Principle #26Copying

Data Source

PatentUS9170841B2Multiprocessor system for comparing execution order of tasks to a failure pattern

Publication Date: 2015.10.27 PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO LTD

AI summary

A multiprocessor system includes a plurality of processors, each including a task scheduler that determines a task execution order of tasks in a task set to be executed by the processors within a task period which is defined as a period in repeated execution of the task sets; and a scheduler management device having a command unit configured to issue a command for at least one of the task schedulers to change the task execution order, wherein each of the at least one of the task schedulers, when receiving the command from the command unit, changes the task execution order of the corresponding processor.