Streaming Multiprocessor Task Scheduling via State Analysis
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Solution Overview
Problem
Conventional scheduling of compute tasks in multiple processor systems relies on application programs or drivers, leading to delays due to interaction between the driver and multiple processors.
Innovation Solution
A method for dynamically scheduling compute tasks by analyzing processor state data to select eligible processors based on availability, without requiring software or driver interaction, and issuing work through a cooperative thread array (CTA).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional scheduling relies on application programs or drivers to schedule compute tasks, then the scheduling mechanism can be implemented with existing software infrastructure, but execution delays occur due to interaction between the driver and multiple processors
Solution Approach 1:
The system enables processors to autonomously manage task scheduling by reading their own state data and determining eligibility to receive work, eliminating the need for continuous driver intervention. Each processor independently monitors its own state and participates in the scheduling decision process without requiring external software coordination.
Solution Approach 2:
The patent replaces the software-based driver mechanism with a hardware-level state analysis mechanism. Processors use their own state data and availability values to determine scheduling eligibility, substituting the conventional software driver approach with a more direct hardware-state-based selection process that occurs without software intervention.
2Ease of operation
If driver interaction is required for scheduling compute tasks, then software control over task assignment is maintained, but system performance is reduced due to additional interaction overhead
Solution Approach 1:
The scheduling decision-making capability is extracted from the software driver and transferred to the hardware level. Processors independently analyze their own state data and availability, removing the bottleneck of driver-mediated communication while preserving the ability to control task assignment through hardware-state mechanisms.
Solution Approach 2:
The patent introduces state data and availability values as intermediaries between the scheduling decision and task execution. These hardware-level state indicators enable processors to communicate their readiness and eligibility without requiring full software driver interaction, acting as a bridge that maintains control while reducing overhead.
3Device complexity
If processors wait for driver scheduling decisions, then centralized task management is maintained, but processor utilization efficiency is reduced
Solution Approach 1:
The system transitions from static centralized scheduling to dynamic distributed state-based scheduling. Processors continuously update their own state data and availability values, enabling real-time adaptive scheduling decisions that respond to changing hardware conditions without requiring centralized intervention.
Solution Approach 2:
Processors perform preliminary self-assessment by analyzing their own state data and determining eligibility before actual task assignment occurs. This advance preparation allows the scheduling system to make faster, more informed decisions about which processors should receive work, improving utilization efficiency.
Data Source
AI summary
One embodiment of the present invention sets forth a technique for selecting a first processor included in a plurality of processors to receive work related to a compute task. The technique involves analyzing state data of each processor in the plurality of processors to identify one or more processors that have already been assigned one compute task and are eligible to receive work related to the one compute task, receiving, from each of the one or more processors identified as eligible, an availability value that indicates the capacity of the processor to receive new work, selecting a first processor to receive work related to the one compute task based on the availability values received from the one or more processors, and issuing, to the first processor via a cooperative thread array (CTA), the work related to the one compute task.