Multiprocessor Time-Sliced Memory Scalability
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Solution Overview
Problem
Multiprocessor arrangements using time-sliced memory are limited in the number of processors that can share information, as the clock frequency ratio between memory and processors restricts scalability, allowing only a few processors to communicate effectively.
Innovation Solution
Implementing a multiprocessor arrangement with multiple memory blocks operating at different clock rates, allowing processors to access different memory blocks through sequential time-slicing, enabling efficient communication among a larger number of processors by creating a multi-dimensional time-slicing scheme where each processor can access multiple memory blocks, thereby overcoming the limitations of traditional one-dimensional time-slicing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional time-sliced memory is used with a single memory block, then memory can operate at a faster clock cycle than processors, but the number of processors that can share information is limited
Solution Approach 1:
The memory system is segmented into multiple memory blocks (first group and second group) that can be independently accessed by different processors. This segmentation allows multiple processors to simultaneously access different memory blocks, thereby increasing the number of processors that can share information while maintaining fast memory operation speeds.
Solution Approach 2:
The patent transitions from one-dimensional time-slicing (single memory block with sequential processor access) to multi-dimensional time-slicing by introducing multiple memory blocks that can be accessed in parallel. This dimensional expansion allows processors to access memory in both time and space dimensions, significantly increasing system capacity.
2Ease of operation
If multiple processors access the same memory block through time-slicing, then communication between processors is enabled, but the clock frequency ratio between memory and processors restricts scalability
Solution Approach 1:
Each memory block is designed to be universally accessible by multiple processors through time-slicing, enabling any processor to communicate with any other processor via shared memory blocks. This multi-functional design allows the system to scale by adding more processors while maintaining communication capabilities through the existing memory infrastructure.
3Use of energy by moving object
If a single memory block is shared by multiple processors, then power and space usage is optimized, but the number of processors is limited by the clock frequency ratio
Solution Approach 1:
The memory system is divided into multiple blocks that can be independently managed and accessed. This segmentation allows the system to support more processors by distributing access across multiple blocks, while each block maintains efficient power usage through targeted access patterns and time-slicing techniques.
Data Source
AI summary
A multiprocessor arrangement is disclosed, in which a plurality of processors are able to communicate with each other by means of a plurality of time-sliced memory blocks. At least one, and up to all, of the processors may be able to access more than one time-sliced memories. A mesh arrangement of such processors and memories is disclosed, which may be a partial or complete mesh. The mesh may to two-dimensional, or higher dimensional.A method of communication between processors in a multiprocessor arrangement is also disclosed, in which one or more processors are able to each access a plurality of memories, in each case by time-slicing.