Multiprocessor Vector Engine with Memory Aggregate Unit
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Solution Overview
Problem
Traditional multiprocessor devices face inefficiencies in program division, inter-processor data transmission, and productivity due to complex hardware requirements and increased costs, especially when handling increased pipeline stages and operating frequencies.
Innovation Solution
A multiprocessor device with an external memory, multiple processors, a memory aggregate unit, register memory, multiplexer, and overall control unit, where a large logical register is used to manage memory accesses, allowing for flexible adjustment of operations and parallel processing without requiring explicit program division, and utilizing a multiplexer to manage register access commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of vector processing engines is increased to improve performance, then processing capacity increases, but memory access becomes concentrated and performance deteriorates due to bandwidth restrictions
Solution Approach 1:
The patent implements dynamic program distribution across vector processing engines, where the control unit assigns different programs or time-staggered execution to each engine. This dynamic allocation prevents simultaneous memory access concentration while maintaining high processing capacity, resolving the contradiction between productivity and memory access efficiency.
2Device complexity
If the vector processing unit is limited to reduce complexity, then circuit scale is reduced, but the ability to handle complex algorithms decreases
Solution Approach 1:
The patent segments the vector processing functionality into multiple simple vector processing engines, each with reduced circuit complexity. By distributing the processing workload across multiple segmented units rather than using a single complex engine, the system achieves both reduced individual circuit scale and maintained overall algorithm handling capability through parallel processing.
Solution Approach 2:
The patent creates universal vector processing engines that can execute multiple types of algorithms through software programming rather than dedicated hardware for each algorithm. This multi-functionality approach allows simple circuit designs to handle diverse algorithms, resolving the contradiction between device complexity and adaptability.
3Ease of operation
If automatic data exchange mechanism is implemented to simplify programming, then programming ease increases, but device complexity and cost increase
Solution Approach 1:
The patent merges the data exchange control functionality into the existing control unit that manages vector processing engine operations. By combining program distribution and data exchange control in a single control unit rather than adding separate hardware mechanisms, the system achieves automatic data exchange that simplifies programming without proportionally increasing device complexity.
Data Source
AI summary
A multiprocessor device includes external memory, processors, a memory aggregate unit, register memory, a multiplexer, and an overall control unit. The memory aggregate unit aggregates memory accesses of the processors. The register memory is prepared by a number equal to the product of the number of registers managed by the processors and the maximum number of processes of the processors. The multiplexer accesses the register memory according to a command given against register access of the processors. The overall control unit extracts a parameter from the command and provides the parameter to the processors and multiplexer, and controls them, as well as has a given number of processes consecutively processed using the same command while having addressing for the register memory changed by the processors, and when the given number of processes ends, has the command switched to a next command and processing repeated for a given number of processes.