Multi-Protocol Interface Pin Sharing for On-Chip Debug Access
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Solution Overview
Problem
Advanced wafer lithography and surface-mount packaging technologies lead to complex integrated circuits with diminished physical access for testing and debugging, resulting in reduced visibility and control, increased design complexity, and higher costs, making it difficult to detect manufacturing defects and ensure system functionality.
Innovation Solution
The integration of on-chip debug facilities with configurable emulation capabilities, including real-time data exchange and trace functions, allows for dynamic pin sharing and selection logic to enable efficient debugging and testing, balancing cost and performance needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If advanced wafer lithography and surface-mount packaging technology are used to integrate increasingly complex functions, then system performance and integration level are improved, but physical access for test and debugging is diminished
Solution Approach 1:
The patent segments the integrated circuit into multiple operational units (first operational unit, second operational unit, etc.), each capable of independent testing and debugging through separate data paths. This allows test access to specific functional blocks without requiring physical access to the entire dense circuit, resolving the contradiction between high integration and testability.
Solution Approach 2:
The patent introduces a data input/output structure that acts as an intermediary between external test equipment and internal operational units. This mediator provides controlled access to operational units, enabling debugging of highly integrated circuits without direct physical access to internal components.
2Adaptability or versatility
If denser designs and shrinking interconnect pitch are implemented, then device functionality is improved, but test and emulation access is reduced
Solution Approach 1:
The patent divides the circuit into discrete operational units with individual data input/output paths. This segmentation allows test equipment to access and debug specific functional blocks through dedicated interfaces, making testing feasible despite shrinking interconnect pitch and dense packaging.
Solution Approach 2:
The patent adds a temporal dimension to testing by implementing stall mode capability, allowing operational units to be frozen at specific states for observation. This enables debugging of high-speed circuits by capturing and analyzing intermediate states without requiring physical access to fast-moving signals.
3Adaptability or versatility
If design complexity increases, then system capabilities are improved, but manufacturing defect detection becomes more difficult
Solution Approach 1:
The patent segments the complex design into operational units that can be independently tested. Each unit has dedicated data input/output paths, allowing manufacturing defects to be detected and localized to specific functional blocks, simplifying quality control in complex systems.
Solution Approach 2:
The patent implements bidirectional data paths between operational units and external interfaces, enabling feedback mechanisms for defect detection. Test equipment can stimulate operational units and observe responses, providing feedback loops that facilitate manufacturing defect detection in complex designs.
4Ease of operation
If on-chip debug facilities are added, then visibility and control are improved, but device complexity increases
Solution Approach 1:
The patent implements a universal data input/output structure that serves multiple operational units through a standardized interface. This multi-functional approach provides visibility and control for debugging without requiring separate complex infrastructure for each operational unit, reducing overall debug facility complexity.
Solution Approach 2:
The patent merges the data input/output structures of multiple operational units into a shared interface framework. By combining common debugging infrastructure with unit-specific operational logic, the patent achieves high visibility and control while minimizing the complexity overhead of debug facilities.
Data Source
AI summary
This invention is an integrated circuit having at least one data pin connecting to external circuits. The invention includes a plurality of operational units each having at least one data input/output for data transfer and an enable input. The operational unit have a normal mode and a stall mode controlled by an enable input. The operational units can exchange data via the data input/output in normal mode and are not capable of exchanging data in the stall mode. A selection logic selectively enables an operation unit and connects the data input/output of the enabled operation unit to the at least one data pin. The selection logic is responsive to external signals on at least one data pin to selectively enable operation units.