Multi-pulse programming reduces memory cell write latency
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Solution Overview
Problem
Current memory devices, such as multi-level cell (MLC) flash memory, require lengthy programming times due to the sequential application of single pulses in programming loops, which hinders faster operation and efficiency.
Innovation Solution
Implementing multi-pulse programming techniques where multiple pulses are applied in each programming loop, with individual pulses corresponding to different voltage levels, allowing for iterative verification and voltage increase in subsequent loops to achieve target programming levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If single pulse programming is used in sequential loops, then programming reliability is maintained, but programming time increases significantly
Solution Approach 1:
The programming process is segmented into multiple pulses within a single loop, where each pulse corresponds to a specific voltage level. This allows parallel progression through voltage levels rather than sequential looping, reducing overall programming time while maintaining reliability through structured pulse verification.
Solution Approach 2:
The control circuit applies multiple pulses in advance within each programming loop, preparing the memory cells to reach target voltage levels more efficiently. By pre-applying multiple voltage-level pulses before verification, the system reduces the number of loops needed and accelerates the programming process.
2Speed
If multiple pulses are applied in each programming loop, then programming speed increases, but verification complexity increases
Solution Approach 1:
The control circuit incorporates verification steps between each pulse application, using feedback to determine whether the memory cells have reached the desired voltage levels. This feedback mechanism simplifies verification by systematically checking each pulse's effect, making the complex multi-pulse process manageable and reliable.
3Manufacturing precision
If iterative verification and voltage increase are performed, then programming precision is achieved, but operational time increases
Solution Approach 1:
The programming process dynamically adjusts the number of pulses and verification steps based on real-time conditions. The control circuit adapts the programming sequence to achieve target voltage levels with minimal iterations, balancing precision requirements with operational time efficiency by applying more pulses only when necessary.
Data Source
AI summary
Embodiments of the present disclosure include techniques and configurations for multi-pulse programming of a memory device. In one embodiment, a method includes applying multiple pulses to program one or more multi-level cells (MLCs) of a memory device, wherein individual pulses of the multiple pulses correspond with individual levels of the one or more MLCs and subsequent to applying the multiple pulses, verifying the programming of the individual levels of the one or more MLCs. Other embodiments may be described and/or claimed.