Multipurpose Arithmetic Unit with Shared Multiplier Circuits

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Solution Overview

Problem

Conventional graphics processing units are specialized and inefficient, as they require multiple dedicated functional units for various operations, leading to increased chip area, cost, and power consumption, while lacking the capability for double-precision operations needed for general-purpose computations.

Innovation Solution

A multipurpose arithmetic functional unit that supports a variety of operations, including filtering, function approximation, and double-precision arithmetic, using shared multiplier and adder circuits to perform operations like linear filtering, double-precision multiplication, and single-precision planar interpolation, allowing for efficient execution of multiple operations with reduced hardware complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple dedicated functional units are used for various operations, then operation specialization and execution efficiency are improved, but chip area, cost, and device complexity increase

Engineering Contradiction:
Improveoperation execution efficiencyVSAvoidchip area and design complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a multipurpose functional unit that can perform multiple operations including single-precision arithmetic, double-precision arithmetic, and filtering operations using a single integrated circuit structure. The unit uses shared multiplier and adder circuits that are dynamically configured through control signals to execute different operations, eliminating the need for separate dedicated functional units for each operation type.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If separate single-precision and double-precision functional units are provided, then precision operation capabilities are improved, but chip area and device complexity increase

Engineering Contradiction:
Improvedouble-precision operation capabilityVSAvoidchip area
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges single-precision and double-precision functional units into a single integrated circuit. The multiplier and adder circuits are designed with sufficient width and precision to handle double-precision operations, while also being capable of performing single-precision operations by utilizing only the necessary portions of the circuits. Control logic dynamically configures the circuit behavior based on the required precision.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If specialized functional units are used for each operation, then operation accuracy and performance are improved, but power consumption and cost increase

Engineering Contradiction:
Improveoperation accuracyVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The multipurpose functional unit maintains high operation accuracy by implementing precisely designed multiplier and adder circuits that can accurately perform all supported operations. The same high-precision circuits are reused across different operations and precision levels, ensuring consistent accuracy while reducing the total number of circuits required, thereby lowering power consumption.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8051123B1Multipurpose functional unit with double-precision and filtering operations
Publication Date: 2011.11.01 NVIDIA CORP
  • US8051123B1 patent drawing
  • US8051123B1 patent drawing
  • US8051123B1 patent drawing

AI summary

A multipurpose arithmetic functional unit selectively performs planar attribute interpolation, unary function approximation, double-precision arithmetic, and/or arbitrary filtering functions such as texture filtering, bilinear filtering, or anisotropic filtering by iterating through a multi-step multiplication operation with partial products (partial results) accumulated in an accumulation register. Shared multiplier and adder circuits are advantageously used to implement the product and sum operations for unary function approximation and planar interpolation; the same multipliers and adders are also leveraged to implement double-precision multiplication and addition.