Multi-Rate Receiver Clock Reconfiguration for Arbitrary Data Rates
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Solution Overview
Problem
Conventional transceiver circuitry is limited to specific data rates, making it inadequate for supporting the entire operating range of standards like HDMI, which requires arbitrary clock rates, and existing solutions using phase-locked loops with wide tuning ranges are costly.
Innovation Solution
The transceiver circuitry is reconfigured to operate at different data rates by receiving a reference clock signal, detecting its frequency, and adjusting the clock generation and receiver circuits accordingly, using rate detection and configuration circuitry to accommodate changes in data rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If transceiver circuitry uses predetermined operating rates, then the circuit design is simple and cost-effective, but the transceiver cannot support the entire operating range of multi-rate protocols like HDMI
Solution Approach 1:
The transceiver circuitry is divided into multiple parallel data path configurations, each optimized for specific data rate ranges. The system segments the overall data rate support into discrete operational modes (e.g., different lane configurations, clock rate ranges) and selects the appropriate segment based on the detected input signal characteristics, allowing broad adaptability without requiring a single complex circuit to handle all rates simultaneously
Solution Approach 2:
The transceiver employs dynamic reconfiguration capability where circuit parameters such as clock rate, lane count, and data rate are adjusted based on the detected input signal. The system dynamically switches between predetermined data path configurations during operation, enabling the same physical hardware to adapt to different data rate requirements without manual reconfiguration or complex wide-tuning PLL circuits
2Adaptability or versatility
If transceiver circuitry uses a phase-locked loop with wide tuning range to support arbitrary data rates, then the adaptability to different HDMI standards is improved, but the cost increases significantly
Solution Approach 1:
The transceiver circuitry is designed with universal support for multiple protocols and data rate ranges through a set of predetermined data path configurations. Rather than requiring specialized wide-tuning PLL circuits for each protocol, the same physical hardware can be configured to support HDMI, DisplayPort, and other protocols across broad data rate ranges by selecting appropriate predetermined configurations, reducing component costs while maintaining universal compatibility
Solution Approach 2:
The system changes operational parameters such as clock rate, data rate, and lane configuration based on the detected input signal characteristics. By detecting the input clock rate and signal format, the transceiver automatically adjusts its operational parameters to match the required protocol and data rate, eliminating the need for expensive wide-tuning PLL circuits while maintaining support for arbitrary data rates within the supported range
Data Source
AI summary
Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include rate detection circuitry, receiver circuitry, and configuration circuitry. The receiver circuitry may receive a data stream with an arbitrary data rate. The rate detection circuitry may receive a reference clock signal that is associated with the received data stream. The rate detection circuitry determines the frequency of the reference clock signal such that an appropriate clock signal may be generated for the receiver circuitry. The receiver clock signal may be generated by clock generation circuitry that is coupled to the rate detection circuitry. The configuration circuitry may accordingly configure the receiver circuitry based at least on the determined frequency of the reference clock signal so that the receiver circuitry may operate at the arbitrary data rate.