Configurable Multirate FIR Filter Using Multiplier-Free Arithmetic
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Solution Overview
Problem
Existing digital signal processing systems require multiple filter banks to process signals with different characteristics, leading to increased power consumption due to inefficient use of resources.
Innovation Solution
A finite impulse response (FIR) filter system with a configurable delay line and arithmetic units that receive control words specifying trivial multiplication and bit shift operations, allowing dynamic configuration to process various signals efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple filter banks are used to process signals with different characteristics, then signal processing capability and adaptability are improved, but power consumption increases
Solution Approach 1:
The patent implements a single FIR filter that can be dynamically configured to process multiple different signals by loading different coefficient sets. The filter hardware remains universal and can adapt to various signal characteristics (different data rates, filter orders, and coefficient values) without requiring separate dedicated filter banks for each signal type, thereby reducing overall power consumption while maintaining signal processing capability.
Solution Approach 2:
The patent employs dynamic configuration of the FIR filter through coefficient loading mechanisms that allow the filter to adapt its characteristics in real-time. The filter can change its coefficients, data rate, and order dynamically based on the input signal requirements, enabling one filter to replace multiple static filter banks while consuming less power.
2Adaptability or versatility
If multiple filter banks are used to process different signals, then versatility is improved, but device complexity increases
Solution Approach 1:
The patent creates a universal FIR filter architecture that can handle multiple signal types and configurations through software-controlled coefficient loading. Instead of implementing multiple separate filter banks with dedicated hardware for each, the system uses one configurable filter with programmable coefficients, significantly reducing system complexity while maintaining the ability to process various signals with different characteristics.
3Measurement precision
If traditional multiplication operations are used in arithmetic units, then calculation precision is improved, but power consumption and computational complexity increase
Solution Approach 1:
The patent transforms the multiplication operation into a series of bit shift operations and additions. By representing coefficients in a format that enables this transformation (such as using integer representations or specific fixed-point formats), the system maintains calculation precision while dramatically reducing power consumption and computational complexity, as bit shifts are much more energy-efficient than traditional multiplication operations.
Solution Approach 2:
The patent replaces the mechanical multiplication operation with a combination of bit shift operations and additions. This substitution leverages the fact that bit shifts are simpler, faster, and more power-efficient operations that can be implemented with fewer hardware resources while maintaining the essential functionality of multiplication through mathematical equivalence.
Data Source
AI summary
A finite impulse response (FIR) filter including a delay line and a plurality of arithmetic units. Each arithmetic unit is coupled to a different one of a plurality of tap points of the delay line, is configured to receive a respective signal value over the delay line, and is associated with a respective coefficient. Any given one of the arithmetic units is configured to receive a respective control word. The respective control word specifying: (i) a plurality of trivial multiplication operations, and (ii) a plurality of bit shift operations. Any given one of the arithmetic units is further configured to estimate or calculate a product of the respective signal of the arithmetic unit respective signal value and the respective coefficient of the arithmetic unit by performing the trivial multiplication operations and bit shift operations that are specified by the respective control word that is received at the given arithmetic unit.