Multi-Rate Sensor I-ADC Circuit for Low-Noise Low-Power Sensing

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Solution Overview

Problem

Existing sensor devices, such as acoustic sensors and microphones, face challenges in reducing noise while maintaining low power consumption, which affects their quality and robustness due to constraints on dimensions and power usage.

Innovation Solution

An integrated circuit with a transconductance element and a multi-rate current-input analog-to-digital converter (I-ADC) that includes continuous-time and discrete-time integrator stages, along with a feedback digital-to-analog converter, to generate a digital sensor signal, reducing noise and power consumption by attenuating high-frequency noise and optimizing signal transfer functions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If noise reducing measures are implemented in sensor devices, then sensor quality and robustness are improved, but power consumption increases

Engineering Contradiction:
Improvesensor quality and robustnessVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The integrator is divided into two distinct stages: a continuous-time integrator stage and a discrete-time integrator stage. This segmentation allows each stage to handle specific aspects of noise reduction independently, optimizing the balance between noise reduction and power consumption by assigning different operational characteristics to each stage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The circuit alternates between continuous-time operation (for noise attenuation) and discrete-time operation (for signal processing). The periodic switching between these modes enables effective noise reduction while managing power consumption through controlled activation of different circuit components at different times.

Inventive Principle:
Principle #19Periodic action

2Volume of moving object

If compact dimensions are used in sensor devices, then device size is reduced, but noise reduction capability is compromised

Engineering Contradiction:
Improvedevice sizeVSAvoidnoise
Core Design Contradiction:
Volume of moving objectVSObject-affected harmful factors

Solution Approach 1:

The continuous-time and discrete-time integrator stages are merged into a single integrated circuit structure, sharing common components such as switches, capacitors, and control logic. This merging enables effective noise reduction through dual-stage processing while maintaining compact dimensions by eliminating redundant components.

Inventive Principle:
Principle #5Merging (Combining)

3Measurement precision

If high-frequency noise attenuation is implemented, then signal quality is improved, but circuit complexity increases

Engineering Contradiction:
Improvesignal qualityVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The circuit changes the operational parameters of the integrator between continuous-time and discrete-time modes to achieve high-frequency noise attenuation. By adjusting the timing and operational state of switches and capacitors, the circuit achieves superior signal quality without requiring additional complex filtering components.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11743647B2Multi-rate integrated circuit connectable to a sensor
Publication Date: 2023.08.29 KNOWLES ELECTRONICS LLC
  • US11743647B2 patent drawing
  • US11743647B2 patent drawing
  • US11743647B2 patent drawing

AI summary

An integrated circuit connectable to a sensor includes a transconductance element and a current-input analog-to-digital converter (I-ADC). The transconductance element is connectable to the sensor and is configured to generate a current signal representative of an output of the sensor. The I-ADC is configured to sample and quantize the current signal to generate a corresponding digital sensor signal. The I-ADC includes a continuous-time (CT) integrator stage, a discrete-time (DT) integrator stage, and a feedback digital-to-analog converter (FB-DAC). The CT integrator stage is configured to receive the current output and the I-ADC is configured to generate the digital sensor signal based on an output of the CT integrator stage and an output of the DT integrator stage. The FB-DAC is configured to provide a feedback signal based on the digital sensor signal for adding to the current signal.