Multirate SerDes Sampling Conversion With Fixed PLL and Interpolation
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Solution Overview
Problem
Current SerDes systems face challenges in achieving back-compatibility for rational sampling rate disparities between new and old-generation products, leading to increased hardware complexity and cost due to the need for multiple PLLs or tunable PLLs, which result in parasitic jitter and phase noise.
Innovation Solution
A method utilizing a Phase Locked Loop (PLL) operating at a fixed frequency coupled with an interpolation filter that performs zero-stuffing, filtering, and decimation to achieve sampling rate conversion, allowing for efficient handling of multiple symbol rates while maintaining a uniform number of samples per symbol.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple PLLs or tunable PLLs are used to handle rational sampling rate disparities, then back-compatibility between new and old-generation products is achieved, but hardware complexity and cost increase
Solution Approach 1:
The patent implements a single fixed-frequency PLL that serves multiple sampling rate requirements by combining it with an interpolation filter. The interpolation filter performs sampling rate conversion to accommodate different symbol rates (e.g., 25.78125 Gs/s for new generation and 16.75 Gs/s for older generation), allowing one PLL to replace what would traditionally require multiple PLLs or tunable PLLs, thus reducing hardware complexity while maintaining back-compatibility
Solution Approach 2:
The interpolation filter acts as an intermediary between the fixed-frequency PLL and the symbol generator. It performs zero-stuffing, filtering, and decimation to convert the PLL's fixed-frequency output to the required variable symbol rates. This intermediary component enables the fixed PLL to interface with different symbol rates without requiring the PLL itself to be tunable or multiplied
2Adaptability or versatility
If multiple PLLs or tunable PLLs are used to handle rational sampling rate disparities, then back-compatibility between new and old-generation products is achieved, but cost increases
Solution Approach 1:
The patent implements a single fixed-frequency PLL that serves multiple sampling rate requirements by combining it with an interpolation filter. The interpolation filter performs sampling rate conversion to accommodate different symbol rates (e.g., 25.78125 Gs/s for new generation and 16.75 Gs/s for older generation), allowing one PLL to replace what would traditionally require multiple PLLs or tunable PLLs, thus reducing hardware complexity while maintaining back-compatibility
Solution Approach 2:
The patent replaces expensive, complex PLL hardware with a simpler fixed-frequency PLL combined with a software-based or firmware-based interpolation filter. The interpolation filter, implemented as a computational algorithm (performing zero-stuffing, filtering, and decimation), is much cheaper to implement than additional hardware PLLs, effectively substituting expensive hardware with less expensive computational processing
3Adaptability or versatility
If tunable PLLs are used to handle sampling rate conversions, then multiple sampling rates are supported, but parasitic jitter and phase noise increase
Solution Approach 1:
The patent implements a single fixed-frequency PLL that serves multiple sampling rate requirements by combining it with an interpolation filter. The interpolation filter performs sampling rate conversion to accommodate different symbol rates (e.g., 25.78125 Gs/s for new generation and 16.75 Gs/s for older generation), allowing one PLL to replace what would traditionally require multiple PLLs or tunable PLLs, thus reducing hardware complexity while maintaining back-compatibility
Solution Approach 2:
The patent replaces the mechanical/electrical tuning mechanism of tunable PLLs with a digital signal processing approach using an interpolation filter. Instead of adjusting the PLL's frequency through hardware tuning (which introduces jitter and phase noise), the system uses a fixed-frequency PLL combined with computational filtering and decimation to achieve variable sampling rates, substituting hardware tuning with software-based signal processing
Data Source
AI summary
A method for providing back-compatibility for rational sampling rate disparities between two circuitries, comprises: a) providing a Phase Locked Loop (PLL) operating at a rate different than that of the Symbols generator, which is coupled to a Digital to Analog Converter (DAC) or an Analog to Digital Converter (ADC); b) providing an interpolation filter coupled to said converter, which filter is adapted to perform sampling rate conversion operations on the samples using zero-stuffing, filtering, and decimation, or the like computation-saving algorithm; and c) obtaining the sampling of the symbols at the required and compatible rate.