Multi-Rate Transceiver Clock Reconfiguration for Arbitrary Data Rates
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Solution Overview
Problem
Conventional transceiver circuitry is limited to specific data rates, making it inadequate for supporting the entire operating range of standards like HDMI, which requires arbitrary clock rates, and existing solutions using phase-locked loops with wide tuning ranges are costly.
Innovation Solution
The development of transceiver circuitry that can be reconfigured to operate at different data rates by receiving a reference clock signal, detecting its frequency, and adjusting the clock generation and receiver circuits accordingly, using rate detection and configuration circuitry to accommodate changes in data rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If transceiver circuitry operates at predetermined data rates, then the circuit design is simple and cost-effective, but the transceiver cannot support the entire operating range of multi-rate protocols like HDMI
Solution Approach 1:
The transceiver circuitry is designed with dynamic reconfiguration capability, allowing it to adapt its operating parameters (data rate, clock frequency) based on the detected input signal characteristics. The circuit can switch between different operating modes to support multiple data rates within the HDMI protocol range, transforming a static predetermined-rate design into a dynamic multi-rate system.
Solution Approach 2:
The invention changes the operating parameters of the transceiver circuitry by detecting the frequency of the incoming reference clock signal and reconfiguring the circuit to operate at the detected data rate. This parameter adaptation allows the same hardware to support multiple data rates (e.g., 25 MHz to 600 MHz pixel clock rates) without requiring separate dedicated circuits for each rate.
2Adaptability or versatility
If a phase-locked loop with wide tuning range is used to support arbitrary data rates, then the transceiver can meet requirements of different HDMI applications, but the solution becomes costly
Solution Approach 1:
The invention replaces expensive phase-locked loop components with a more cost-effective detection and reconfiguration approach. By using frequency detection circuitry to identify the incoming data rate and then reconfiguring the transceiver accordingly, the system achieves the same adaptability without the high manufacturing cost associated with wide-tuning-range PLLs.
Solution Approach 2:
The transceiver system performs self-configuration by automatically detecting the frequency of the incoming reference clock signal and adjusting its own operating parameters to match the detected data rate. This self-service capability eliminates the need for external complex PLL circuitry, reducing manufacturing costs while maintaining full HDMI protocol compatibility.
3Ease of manufacture
If transceiver circuitry is designed for specific data rates, then the circuit is easier to manufacture, but it limits the transceiver's ability to support various input-output interfaces with different data rates
Solution Approach 1:
The transceiver circuitry is designed with universal reconfiguration capability, allowing a single hardware design to support multiple input-output interfaces and data rates. By detecting the incoming signal characteristics and adapting its operating parameters, the circuit achieves multi-functionality, supporting HDMI and other protocols across a wide data rate range without requiring separate dedicated circuits for each interface.
Data Source
AI summary
Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include rate detection circuitry, receiver circuitry, and configuration circuitry. The receiver circuitry may receive a data stream with an arbitrary data rate. The rate detection circuitry may receive a reference clock signal that is associated with the received data stream. The rate detection circuitry determines the frequency of the reference clock signal such that an appropriate clock signal may be generated for the receiver circuitry. The receiver clock signal may be generated by clock generation circuitry that is coupled to the rate detection circuitry. The configuration circuitry may accordingly configure the receiver circuitry based at least on the determined frequency of the reference clock signal so that the receiver circuitry may operate at the arbitrary data rate.