Multi-row QFN Package with Exposed Lead Ends
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Solution Overview
Problem
Conventional quad flat non-leaded (QFN) semiconductor packages face challenges in achieving high I/O density and efficient solder inspection due to low I/O density and issues with traditional wire bond processes, which hinder production yields and electrical performance.
Innovation Solution
A multi-row, sawed-type QFN semiconductor package with lead terminals arranged in a triple row configuration, featuring exposed base metal on cut ends and a staggered layout, along with a molding compound encapsulation and connection tie-bars, to enhance wire bonding and solder inspection visibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional aQFN packages are used to achieve high I/O density, then I/O density is improved, but solder inspection becomes difficult due to hidden solder joints
Solution Approach 1:
The lead terminals are segmented into multiple rows (first, second, and third rows) with different lengths and exposure positions. This segmentation allows the solder joints to be distributed at different locations, with at least some being visible for inspection while maintaining high I/O density through the multi-row configuration
Solution Approach 2:
The invention transitions from a traditional single-row or dual-row configuration to a multi-row configuration with lead terminals extending along multiple sides of the package. This dimensional change in the arrangement of lead terminals enables both high I/O density and visible solder joints for inspection
2Device complexity
If traditional wire bond processes are used in nonleaded designs, then manufacturing simplicity is maintained, but production yield decreases due to unique land site geometry and form factor density
Solution Approach 1:
The invention changes the geometric parameters of the lead terminals, specifically creating a multi-row configuration with varying terminal lengths and exposure positions. This parameter change in the land site geometry makes the wire bond process more compatible with nonleaded designs, improving production yield while maintaining manufacturing simplicity
3Area of stationary object
If package size is reduced to meet miniaturization demands, then area occupied is reduced, but wire bond length increases leading to degraded electrical performance
Solution Approach 1:
The invention arranges lead terminals in multiple rows along different sides of the package rather than concentrating them in a single area. This multi-dimensional arrangement allows the semiconductor die to be positioned more centrally, reducing the average wire bond length to lead terminals while maintaining a compact package footprint
Data Source
AI summary
A semiconductor package includes at least one die attach pad of a leadframe, at least one semiconductor die mounted on the at least one die attach pad; and a plurality of lead terminals disposed around the at least one die attach pad and electrically connected to respective input/output (I/O) pads on the at least one semiconductor die through a plurality of bond wires. The plurality of lead terminals comprises first lead terminals, second lead terminals, and third lead terminals, which are arranged in triple row configuration along at least one side of the semiconductor package. Each of the first lead terminals, second lead terminals, and third lead terminals has an exposed base metal on a cut end thereof.