Multirow Video Encoder Architecture for Parallel Block-Row Processing

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Solution Overview

Problem

Existing video encoding techniques result in significant wait times and underutilization of hardware components due to sequential processing, limiting the ability to leverage parallel processing capabilities of CPUs and GPUs, and additional hardware encoders lead to increased surface area and power consumption without enhancing encoding speed.

Innovation Solution

A hardware video encoder architecture that enables parallel encoding of multiple block rows in a media frame by utilizing multiple row control units, allowing concurrent access to hardware computational resources, thereby enhancing parallel processing and resource utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If sequential encoding of blocks is used, then encoding quality is maintained through proper dependency handling, but hardware components experience significant wait times and underutilization

Engineering Contradiction:
Improveencoding qualityVSAvoidwait times
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the video frame into multiple independent row strips that can be encoded in parallel. Each row control unit processes a specific row strip independently, eliminating sequential dependencies between rows while maintaining encoding quality through proper intraframe prediction handling within each strip.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic row control units that can adaptively process different row strips based on available hardware resources and data readiness. The system dynamically allocates processing tasks to multiple control units, optimizing both throughput and resource utilization while maintaining quality requirements.

Inventive Principle:
Principle #15Dynamics

2Productivity

If multiple hardware video encoders are added to encode multiple video streams in parallel, then throughput increases, but integrated circuit surface area and power consumption double or triple

Engineering Contradiction:
Improvevideo stream throughputVSAvoidintegrated circuit surface area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent creates a universal hardware video encoder architecture where multiple row control units share common functional resources such as motion estimation units, transformation units, and quantization units. This multi-functional design allows a single encoder to process multiple video streams in parallel by dividing work across row strips, eliminating the need for separate dedicated encoders for each stream and significantly reducing overall circuit area and power consumption.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If sequential encoding is used, then intraframe prediction dependencies are properly handled, but encoding speed is limited and parallel processing capabilities cannot be utilized

Engineering Contradiction:
Improveintraframe prediction accuracyVSAvoidencoding speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent segments the frame into row strips that can be processed in parallel while maintaining intraframe prediction accuracy within each strip. By carefully managing the segmentation boundaries and prediction dependencies within strips, the system achieves both parallel processing speed and prediction accuracy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces row control units as intermediary components that manage the complex dependencies between intraframe predictions and parallel processing. These control units coordinate data flow and prediction information between parallel processing elements, enabling fast parallel encoding while maintaining prediction accuracy through proper dependency management.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20260046421A1Hardware video encoder architecture for multirow parallel encoding
Publication Date: 2026.02.12 NVIDIA CORP
  • US20260046421A1 patent drawing
  • US20260046421A1 patent drawing
  • US20260046421A1 patent drawing

AI summary

Various embodiments include techniques for parallel encoding of multiple rows of a media frame. The disclosed video encoder includes multiple controllers, where each controller encodes components, or blocks, included in a different row of a media frame. Each of the controllers encodes the respective blocks of the different rows by sending commands and data to different encoding resources that each perform different encoding functions. The controllers have concurrent and independent access to the encoding resources. As a result, the controllers can access any encoding resource to perform encoding functions without regard to what other encoding resources are performing encoding functions for other controllers. As a result, utilization of encoding resources is increased, and encoding performance is improved, relative to conventional techniques.