Multi-Sheet Gate Structure With SiGe Liner for Short-Channel Control
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Solution Overview
Problem
Current semiconductor devices face challenges in scaling and improving performance and reliability, particularly in multi-gate transistors where the short channel effect (SCE) affects channel potential and current control, and there is a need for enhanced integration density and gate length minimization.
Innovation Solution
A semiconductor device design featuring a multi-channel active pattern with a lower pattern and sheet patterns, including gate structures with inner gate structures and a source/drain pattern comprising a semiconductor liner film and filling film made of silicon-germanium, where the liner film protrudes beyond the upper surface of the sheet patterns and has a specific geometric configuration to improve control and reduce SCE.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistor with three-dimensional channel is used, then integration density is improved, but device complexity increases
Solution Approach 1:
The gate structure is segmented into multiple independent gate electrodes (first gate electrode, second gate electrode, third gate electrode) that wrap around the channel from different directions. This segmentation allows each gate to independently control a portion of the channel, achieving effective 3D channel control while maintaining manufacturing feasibility through modular fabrication processes
Solution Approach 2:
The gate structures extend into the vertical dimension, wrapping around the channel in a three-dimensional configuration rather than a planar arrangement. The first gate electrode is positioned at a first height, the second gate electrode at a second height, and the third gate electrode at a third height, creating multi-layered gate control that enables superior channel modulation without requiring excessive planar space
2Productivity
If gate length is reduced for scaling, then current control capability is improved, but short channel effect worsens
Solution Approach 1:
The gate control is extended into the vertical dimension with multiple gate electrodes positioned at different heights wrapping around the channel. This 3D gate configuration provides wrap-around control that effectively suppresses short channel effects even when the lateral gate length is reduced for scaling, as the vertical wrap-around gates maintain electrostatic control over the channel
Solution Approach 2:
The gate structures are nested in multiple layers around the channel, with inner gate electrodes positioned closer to the channel and outer gate electrodes positioned at greater distances. This nested configuration allows progressive control of the channel from multiple radial distances, enhancing short channel effect suppression while maintaining compact device footprint
3Manufacturing precision
If semiconductor liner film with high germanium fraction is used, then manufacturing precision is improved, but material composition control becomes more difficult
Solution Approach 1:
The semiconductor liner film exhibits spatially varying germanium composition, with the germanium fraction being higher in regions adjacent to the gate structures and lower in other regions. This local quality variation is deliberately engineered to provide enhanced manufacturing precision in critical areas (near gates) while maintaining overall device performance, with each region's composition optimized for its specific functional requirements
Data Source
AI summary
A semiconductor device includes an active pattern including a lower pattern extending in a first direction, and a plurality of sheet patterns spaced apart from the lower pattern in a second direction. The sheet patterns include an uppermost sheet pattern and a plurality of gate structures on the lower pattern and spaced apart from each other in the first direction. Each of the plurality of gate structures includes a gate electrode and a gate insulating film and a source/drain pattern between adjacent ones of the plurality of gate structures. Each of inner gate structures includes a gate electrode and a gate insulating film. A semiconductor liner film includes silicon-germanium, and contacts the gate insulating film of each of the inner gate structures. A portion of the semiconductor liner film protrudes upwardly in the first direction beyond an upper surface of the uppermost sheet pattern.