Multi-Sheet Transistor Source/Drain Liners for Short-Channel Control
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Solution Overview
Problem
Current semiconductor devices face challenges in improving device performance and reliability, particularly in multi-gate transistors where scaling and short channel effects are concerns.
Innovation Solution
The semiconductor device incorporates a design with a lower pattern and multiple sheet patterns, featuring gate structures with inner gate structures, source/drain recesses, and semiconductor liners doped with carbon or phosphorus, which enhance current control and reduce short channel effects by optimizing the geometry and doping of the source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistor with 3D channel is used for scaling, then device density and current control capability are improved, but short channel effects become more pronounced
Solution Approach 1:
The patent transitions from planar 2D channel to three-dimensional 3D channel structure by stacking multiple sheet patterns vertically. This dimensional change enables better gate control over the channel while maintaining scalability, as the gate wraps around the channel in multiple dimensions, effectively suppressing short channel effects that plague conventional planar transistors at scaled dimensions
Solution Approach 2:
The patent implements nested gate structures where inner gate structures are positioned between adjacent sheet patterns or between the lower pattern and the adjacent sheet pattern. This nested configuration allows multiple gate structures to control different portions of the 3D channel, providing enhanced electrostatic control and effectively mitigating short channel effects through multi-layered gating
2Ease of manufacture
If conventional source/drain structure is used in multi-gate transistor, then manufacturing is simpler, but device performance and reliability are insufficient
Solution Approach 1:
The patent applies different doping conditions to different regions of the source/drain structure. Carbon doping is applied to specific semiconductor liner regions while other regions remain undoped or differently doped. This local differentiation optimizes electrical properties in critical areas (such as contact regions and channel interfaces) while maintaining manufacturability through selective doping processes
Solution Approach 2:
The source/drain structure employs composite material composition with multiple semiconductor liners having different material properties and doping states. The structure includes carbon-doped semiconductor liners, carbon-undoped semiconductor liners, and filling semiconductor films, creating a composite structure that combines the advantages of different materials to achieve both performance enhancement and manufacturing feasibility
Data Source
AI summary
A semiconductor device comprises an active pattern including a lower pattern and a plurality of sheet patterns that are spaced apart from the lower pattern in a first direction, a plurality of gate structures disposed on the lower pattern to be spaced apart from each other in a second direction, each of the gate structures including a gate electrode and gate insulating films, source/drain recesses defined between adjacent gate structures and a source/drain pattern filling the source/drain recesses. Each source/drain pattern may include a first semiconductor liner, which extend along sidewalls and a bottom surface of the source/drain recesses, second semiconductor liners, which are on the first semiconductor liners and extend along the sidewalls and the bottom surface of the source/drain recesses, and a filling semiconductor film, which is on the second semiconductor liners and fills the source/drain recess. The second semiconductor liners may be doped with carbon, and the first semiconductor liners may be in contact with the lower pattern and the sheet patterns, while the first semiconductor liners may include carbon-undoped regions.