Multi-Slice Processor Load/Store Superslice Parallel Execution
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Solution Overview
Problem
Current computer processors face inefficiencies in processing instructions due to limitations in executing simultaneous two-target loads and stores, which can lead to reduced performance and increased power consumption.
Innovation Solution
A multi-slice processor architecture that includes a load/store superslice with a set predict array, allowing for the execution of two-target load and store instructions in parallel by determining specific subsets of ports for effective address generation, utilizing less logic than a full load/store slice.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a full load/store slice is used to execute two-target load and store instructions simultaneously, then processing capability is improved, but device complexity and power consumption increase
Solution Approach 1:
The processor is divided into multiple load/store slices (first load/store slice, second load/store slice) that can be independently activated. Instead of using a single full-featured load/store slice for all operations, the patent segments the processing capability across multiple simpler slices, allowing selective activation based on instruction type (two-target load vs. store instructions).
Solution Approach 2:
The set predict array serves multiple functions: it determines effective addresses for both two-target load instructions and store instructions, and it can be selectively activated based on the instruction type. This multi-functional component replaces the need for dedicated complex logic in each load/store slice, reducing overall device complexity while maintaining processing capability.
2Productivity
If a full load/store slice is used to execute two-target load and store instructions simultaneously, then processing capability is improved, but power consumption increases
Solution Approach 1:
The processor dynamically activates only the necessary load/store slice based on the instruction type being executed. When a two-target load instruction is detected, the first load/store slice is activated; when a store instruction is detected, the second load/store slice is activated. This dynamic activation reduces power consumption compared to always having a full load/store slice active.
Solution Approach 2:
The set predict array provides universal address generation functionality for both load and store instructions, allowing the processor to use simpler, lower-power logic components instead of a full-featured load/store slice for all operations.
3Productivity
If separate logic is implemented for two-target load and store instructions, then processing efficiency is improved, but device complexity increases
Solution Approach 1:
The set predict array merges the address generation functionality for both two-target load instructions and store instructions into a single shared component. This allows the processor to handle different instruction types efficiently without duplicating complex logic, as the set predict array can be selectively activated based on the instruction type.
Data Source
AI summary
Operation of a multi-slice processor that includes a plurality of execution slices and a load/store superslice, where the load/store superslice includes a set predict array, a first load/store slice, and a second load/store slice. Operation of such a multi-slice processor includes: receiving a two-target load instruction directed to the first load/store slice and a store instruction directed to the second load/store slice; determining a first subset of ports of the set predict array as inputs for an effective address for the two-target load instruction; determining a second subset of ports of the set predict array as inputs for an effective address for the store instruction; and generating, in dependence upon logic corresponding to the set predict array that is less than logic implementing an entire load/store slice, output for performing the two-target load instruction in parallel with generating output for performing the store instruction.