Multislot Link-Layer Flits for Interconnect Flow Control

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Solution Overview

Problem

Current interconnect architectures in high-performance computing systems face challenges in efficiently managing communication between multiple processors and devices, leading to bottlenecks in data transfer and increased power consumption, particularly in servers and mobile devices.

Innovation Solution

The development of a High Performance Interconnect (HPI) architecture that employs a layered protocol stack, including a transaction layer, link layer, and physical layer, with features such as credit-based flow control, virtual channels, and flexible routing, to enable reliable and efficient data transfer across point-to-point links, optimizing bandwidth and power usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If traditional multi-drop buses are used for interconnect, then electrical communication is simplified, but communication speed and performance are limited

Engineering Contradiction:
Improvecommunication speedVSAvoidinterconnect architecture complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent segments the communication protocol into distinct layers (transaction layer, link layer, physical layer) with clearly defined interfaces between them. This segmentation allows each layer to be optimized independently for speed while managing complexity through modular design, enabling high-performance point-to-point communication without overwhelming system complexity.

Inventive Principle:
Principle #1Segmentation

2Productivity

If processing power is increased with multiple cores and sockets, then computing performance improves, but communication between sockets becomes more critical and complex

Engineering Contradiction:
Improvecomputing performanceVSAvoidcommunication architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces virtual channels as an additional dimension for managing communication between multiple sockets and cores. By adding this dimensional layer, the architecture can handle increased communication demands from multi-socket systems without proportionally increasing physical complexity, as virtual channels provide logical organization and resource management.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The link layer acts as an intermediary between the transaction layer and physical layer, managing flow control, error handling, and credit-based resource allocation. This intermediary layer shields upper layers from the complexity of physical communication management, enabling high productivity applications to operate without directly managing communication complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If data transfer rate is increased to meet processing demands, then system performance improves, but power consumption increases

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic flow control mechanisms where credit-based allocation allows data transfer rates to adapt to actual processing needs. When processing demand is high, transfer rates increase; when demand is low, rates decrease accordingly. This dynamic adjustment optimizes data transfer efficiency while minimizing unnecessary power consumption during low-utilization periods.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The credit-based flow control system provides feedback between transmitting and receiving ends, allowing the system to automatically adjust transfer rates based on buffer status and processing capacity. This feedback mechanism ensures high data transfer efficiency when needed while reducing power consumption by throttling transfers when processing capacity is available, eliminating the need for constant maximum-rate operation.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10380059B2Control messaging in multislot link layer flit
Publication Date: 2019.08.13 INTEL CORP
  • US10380059B2 patent drawing
  • US10380059B2 patent drawing
  • US10380059B2 patent drawing

AI summary

A link layer control message is generated and included in a flit that is to be sent over a serial data link to a device. The flits sent over the data link are to include a plurality of slots. Control messages can include, in some aspects, a viral alert message, a poison alert message, a credit return message, and acknowledgements.