Multislot Link-Layer Flits for Bandwidth and Credit Return
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current interconnect architectures in high-performance computing systems face challenges in scaling bandwidth and power efficiency as the complexity of computing systems increases, with existing solutions struggling to meet the demands of both high performance and power savings across various market segments.
Innovation Solution
The development of a High Performance Interconnect (HPI) system that employs a next-generation cache-coherent, link-based interconnect architecture with a layered protocol stack, including a transaction layer, link layer, and physical layer, which supports multiple devices and configurations, and incorporates features like credit-based flow control, virtual channels, and flexible routing to optimize data transfer and power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional multi-drop buses are used for interconnect, then device complexity is reduced, but communication performance and bandwidth scaling are limited
Solution Approach 1:
The interconnect architecture is segmented into multiple independent point-to-point links instead of a shared multi-drop bus. Each link has dedicated bandwidth and can operate independently, enabling parallel data transmission and eliminating the bandwidth sharing limitations of traditional buses while maintaining manageable complexity through modular link design.
Solution Approach 2:
The architecture transitions from a single shared communication dimension (multi-drop bus) to multiple parallel communication dimensions (point-to-point links). This dimensional expansion allows simultaneous data transfer across multiple channels, dramatically increasing aggregate bandwidth without proportionally increasing complexity.
2Power
If multiple physical processors (sockets) are added to increase computing power, then processing capability improves, but communication requirements and interconnect demand increase
Solution Approach 1:
The point-to-point interconnect architecture provides universal connectivity between any pair of sockets and devices through a standardized link layer protocol. This multi-functional interface handles diverse communication needs (data transfer, control signals, flow control) across multiple sockets uniformly, enabling scaling to more processors without proportionally increasing communication complexity.
Solution Approach 2:
The link layer protocol acts as an intermediary between physical processors and devices, abstracting the complexity of multi-socket communication. It provides standardized error checking, flow control, and data framing that simplifies direct communication between sockets while maintaining high performance through dedicated physical links.
3Ease of manufacture
If existing interconnect architectures are used, then implementation simplicity is maintained, but power efficiency and performance scaling are insufficient
Solution Approach 1:
The high-performance point-to-point links enable continuous data transfer without the interruptions and idle periods inherent in shared bus systems. By eliminating bus arbitration and signal sharing, data can flow continuously across dedicated links, improving energy efficiency through reduced idle power consumption while maintaining implementation simplicity through standardized link protocols.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A data link layer generates flits comprising data link layer information, including cyclic redundancy check information. A flit can contain a plurality of slots, wherein one slot can carry a credit return, another can carry data, and unused slots are set to an all zero state.