Multi-Stack Chip Package Parameter Calibration

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Solution Overview

Problem

Multi-stack chip packages in data storage devices face reliability issues due to changes in intrinsic parameters like program voltage caused by thermal and mechanical stress during manufacturing, leading to program errors and increased execution frequency.

Innovation Solution

A method is implemented where each semiconductor chip in a multi-stack chip package has its feature parameters measured and stored, and a controller adjusts these parameters to match the target values designed by the memory vendor, ensuring consistent operation by controlling the chips based on the differences between measured and target feature parameters.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple semiconductor chips are stacked in a multi-stack chip package, then data storage capacity is improved, but parameter consistency deteriorates due to thermal and mechanical stress during manufacturing

Engineering Contradiction:
Improvedata storage capacityVSAvoidparameter consistency
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent applies local quality by measuring and calibrating feature parameters individually for each semiconductor chip in the multi-stack package. Each chip receives customized control parameters based on its specific measured characteristics, rather than applying uniform parameters to all chips. This resolves the parameter consistency issue while maintaining the high storage capacity benefit of multi-chip stacking.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements parameter changes by adjusting control parameters for each semiconductor chip based on measured feature parameters. The controller modifies operating parameters such as program voltage, read voltage, and erase voltage to compensate for variations introduced during the stacking manufacturing process. This ensures each chip operates within optimal parameter ranges despite manufacturing-induced variations.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If feature parameters are measured and calibrated for each semiconductor chip, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improveoperation reliabilityVSAvoidcontrol complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by measuring and storing feature parameters for each semiconductor chip before normal operation begins. The calibration data is captured during manufacturing or initialization, and the controller uses these pre-measured values to determine appropriate control parameters. This upfront measurement approach ensures reliable operation without requiring complex real-time adjustments during normal device operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements self-service by enabling each semiconductor chip to provide its own feature parameter measurements to the controller. Each chip essentially calibrates itself by reporting its measured characteristics, and the controller automatically determines appropriate control parameters based on these self-reported values. This reduces the need for external intervention and simplifies the overall calibration process.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10103129B2Data storage device having multi-stack chip package and operating method thereof
Publication Date: 2018.10.16 SAMSUNG ELECTRONICS CO LTD
  • US10103129B2 patent drawing
  • US10103129B2 patent drawing
  • US10103129B2 patent drawing

AI summary

A data storage device includes a controller and a multi-stack chip package. A method is used to operate the data storage device. The multi-stack chip package includes a first semiconductor chip arranged on a package substrate, a second semiconductor chip arranged on the first semiconductor chip, and a third semiconductor chip is arranged between the first and second semiconductor chips. The controller can control the first to third semiconductor chips by using a feature parameter measured from each semiconductor chip and a target value that may be originally designed by a memory vendor.