Multi-Stack Diffusion Break Layout for Transistor Isolation
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Solution Overview
Problem
In semiconductor device design, achieving high device density while maintaining performance is challenging, particularly in isolating transistors and controlling stress in three-dimensional transistor structures.
Innovation Solution
The implementation of a multi-stack semiconductor device with diffusion break structures selectively formed on both lower and upper stacks, utilizing double diffusion break structures to isolate transistors and control stress, thereby enhancing device density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If double diffusion break structures are formed on both lower and upper stacks to improve isolation and stress control, then device performance is improved, but device density decreases due to increased area occupation
Solution Approach 1:
The patent transitions from two-dimensional planar transistor structures to three-dimensional stacked transistor structures. By forming multiple transistor stacks vertically on the same substrate area, the device density is significantly increased without compromising the isolation and stress control provided by the diffusion break structures at each stack level.
Solution Approach 2:
The patent divides the semiconductor device into multiple independent transistor stacks arranged vertically. Each stack contains complete transistor structures with their own diffusion break structures, allowing independent optimization of isolation and stress control for each stack while maintaining high overall device density through vertical integration.
2Area of moving object
If three-dimensional stacked transistor structures are formed to increase device density, then area utilization is improved, but isolation and stress control become more difficult
Solution Approach 1:
The patent solves the isolation and stress control challenge in three-dimensional structures by introducing diffusion break structures at multiple vertical levels (lower and upper stacks). This multi-level approach maintains effective isolation and stress control despite the increased vertical complexity, enabling high device density without sacrificing reliability.
Solution Approach 2:
The patent applies diffusion break structures selectively at specific locations within each transistor stack (between adjacent gate structures in lower and upper stacks). This localized application ensures that isolation and stress control are optimized precisely where needed in the three-dimensional structure, rather than requiring uniform treatment throughout.
Data Source
AI summary
A multi-stack semiconductor device includes: a plurality of lower transistor structures arranged on a lower stack and including a plurality of lower fin structures surrounded by a plurality of lower gate structures, respectively; a plurality of upper transistor structures arranged on an upper stack and including a plurality of upper fin structures surrounded by a plurality of upper gate structures, respectively; and at least one of a lower diffusion break structure on the lower stack and a upper diffusion break structure on the upper stack, wherein the lower diffusion break structure is formed between two adjacent lower gate structures, and isolates two lower transistor structures respectively including the two adjacent lower gate structures from each other, and the upper diffusion break structure is formed between two adjacent upper gate structures, and isolates two upper transistor structures respectively including the two adjacent upper gate structures from each other.