Multi-Stack FET Power Rail Layout for Lower Contact Resistance

The patent transitions from two-dimensional planar power rail connections to three-dimensional vertical stacking, where power rails are positioned at different vertical levels (first power rail at first level, second power rail at second level) to connect with stacked transistors. This dimensional change enables simultaneous connection to multiple transistor layers, increasing contact area and reducing electrical resistance while maintaining high integration density.

The patent implements a nested structure where transistors are stacked vertically with power rails and via holes integrated into the same vertical column. The first transistor, second transistor, first power rail, and second power rail are all nested within a shared vertical space, allowing multiple functional elements to occupy overlapping horizontal footprints while maintaining distinct vertical positions, thereby reducing overall device area and improving integration.

The patent divides the power distribution network into segmented sections with discrete first and second power rails at different vertical levels, each serving specific transistor layers. This segmentation allows independent optimization and manufacturing of different vertical sections, reducing overall manufacturing complexity while maintaining high integration density.

The patent designs a universal vertical column structure that simultaneously accommodates multiple transistors, power rails, and via holes in a standardized configuration. This multi-functional vertical template can be replicated across the device, simplifying manufacturing processes through standardization while achieving high integration density.