Wraparound Multi-Stack Gate Structure for Short-Channel Control
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Solution Overview
Problem
As integrated circuit technologies progress towards smaller technology nodes, existing techniques for multi-gate devices like FinFETs and gate-all-around transistors face challenges in controlling short channel effects and gate behavior, which impact device performance.
Innovation Solution
A semiconductor structure is developed with a multi-gate device featuring a gate structure that wraps around two or more stacks of channel layers, connected to a shared source/drain feature, improving gate control and reducing short channel effects while enhancing process window and metal gate patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing techniques are used for multi-gate devices, then manufacturing is simpler, but gate control and short channel effect are insufficient
Solution Approach 1:
The channel region is divided into multiple segments stacked vertically to form multi-stack structures. Each stack contains channel layers separated by sacrificial layers, allowing the gate to wrap around multiple channel segments independently. This segmentation improves gate control over each channel portion while managing short channel effects through the stacked configuration.
Solution Approach 2:
The gate structure is configured to wrap around and enclose the channel stacks in a nested arrangement. The gate electrode surrounds the channel regions from multiple sides, creating a gate-all-around configuration that provides enhanced control. The sacrificial layers are nested between channel layers within each stack, enabling selective removal to form the wrapped gate structure.
2Reliability
If gate-all-around behavior is reduced, then device complexity decreases, but controllability by the gate deteriorates
Solution Approach 1:
The gate control is extended from two-dimensional planar control to three-dimensional wraparound control by stacking multiple channel layers vertically. The gate structure wraps around the channel stacks in the vertical dimension, providing controllability from top, bottom, and sidewalls simultaneously. This dimensional transition enhances gate authority over the channel while managing structural complexity through the stacked architecture.
3Productivity
If technology node scaling continues, then production efficiency increases, but short channel effects and gate controllability are impacted
Solution Approach 1:
The channel is segmented into multiple thin stacks vertically, allowing each stack to be controlled independently by the gate. This segmentation enables effective gate control at scaled dimensions where traditional planar structures fail due to short channel effects. The stacked configuration maintains production efficiency by enabling parallel processing of multiple channels while improving reliability through enhanced gate authority.
Data Source
AI summary
A method includes providing a workpiece. The workpiece includes a fin-shaped structure including a fin base and a stack of semiconductor layers over the fin base, a dummy gate structure disposed over the stack of semiconductor layers, and a source/drain feature connected to the channel layers of the stack of semiconductor layers and disposed on a side of the dummy gate structure. The stack of semiconductor layers includes channel layers interleaving with sacrificial layers. The method further includes forming a trench in the dummy gate structure and the fin-shaped structure, depositing a dielectric layer in the trench, depositing a polycrystalline semiconductor material over the dielectric layer, performing a planarization process to the workpiece, and replacing the dielectric layer, the polycrystalline semiconductor material, the dummy gate structure, and the sacrificial layers with a metal gate structure.