Multi-Stack Semiconductor Interconnect Layout for Easier Pad Formation
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Solution Overview
Problem
The complexity and difficulty in forming pad portions increase with the number of vertically stacked interconnection layers in multi-stack semiconductor devices, complicating the process and affecting integration density and electrical characteristics.
Innovation Solution
A semiconductor device with a substrate having a cell region and a connection region, featuring a lower stack structure and an upper stack structure with alternately stacked insulating and interconnection layers, where the extension line portions are designed with specific distances and configurations to simplify the formation of pad portions and enhance integration density and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of vertically stacked interconnection layers is increased to improve integration density, then the integration density is improved, but the process complexity and difficulty of forming pad portions increases
Solution Approach 1:
The interconnection layers are segmented into two distinct groups: extension line portions that extend from gate electrode portions, and pad portions that are formed separately. This segmentation allows the pad portions to be formed through a simplified process while maintaining the multi-stack structure for high integration density.
Solution Approach 2:
The patent transitions from a two-dimensional planar interconnection layout to a three-dimensional multi-stack configuration. By stacking multiple interconnection layers vertically with extension line portions and pad portions at different heights, the design achieves higher integration density while managing process complexity through dimensional organization.
2Quantity of substance
If the number of vertically stacked interconnection layers is increased to improve integration density, then the integration density is improved, but the difficulty of forming pad portions increases
Solution Approach 1:
The interconnection layers are segmented into extension line portions and pad portions, allowing the pad portions to be formed through a simplified process while maintaining the multi-stack structure for high integration density.
Solution Approach 2:
Extension line portions are formed in advance as part of the interconnection layers before the final pad portion formation. This preliminary action simplifies the subsequent pad formation process by pre-establishing the connection pathways.
3Quantity of substance
If the distance between extension line portions is reduced to improve integration density, then the integration density is improved, but the electrical characteristics may be affected
Solution Approach 1:
The patent utilizes vertical stacking to reduce the planar distance between interconnection elements. By organizing extension line portions and pad portions across multiple vertical layers, the design achieves higher integration density while maintaining adequate electrical isolation and characteristics through three-dimensional spatial arrangement.
Solution Approach 2:
Different regions of the multi-stack structure have different characteristics: extension line portions in the cell region have optimized spacing for electrical performance, while pad portions in the connection region are positioned to optimize integration density. This local optimization allows both electrical characteristics and integration density to be improved.
Data Source
AI summary
A semiconductor device includes a substrate having a cell region and a connection region adjacent to the cell region. A lower stack structure and an upper stack structure are disposed on the substrate. A channel structure is provided to pass through the upper stack structure and the lower stack structure. A distance between a lower extension line portion included in an uppermost one of a plurality of lower interconnection layers and an upper extension line portion included in a lowermost one of a plurality of upper interconnection layers is less than a distance between a lower gate electrode portion included in the uppermost one of the plurality of lower interconnection layers and an upper gate electrode portion included in the lowermost one of the plurality of upper interconnection layers.