Multi-Stack Nanosheet Channel Structure With Thick Gate Oxide
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Solution Overview
Problem
The high device density requirement for multi-stack semiconductor devices poses a challenge in forming a gate dielectric layer with sufficient thickness to withstand operating voltages without oxide breakdown, due to limited vertical space between nanosheet channel layers.
Innovation Solution
A multi-stack nanosheet structure is developed, featuring a U-shaped channel structure with a gate dielectric layer of sufficient thickness, allowing for the formation of a field-effect transistor or bipolar junction transistor, where the gate dielectric layer is formed as an extra gate oxide layer with a thickness of about 4-5 nm, enabling high oxide breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate dielectric layer is formed with sufficient thickness (4-5 nm) to withstand operating voltage without oxide breakdown, then the reliability of the semiconductor device is improved, but the device density decreases due to increased vertical space occupation
Solution Approach 1:
The patent transitions from a conventional planar gate structure to a three-dimensional gate-all-around structure that completely surrounds the nanosheet channel. This dimensional change allows the gate dielectric layer to be effectively distributed in multiple directions rather than occupying only vertical space, enabling sufficient dielectric thickness for reliability while maintaining high device density through vertical stacking of multiple nanosheets
Solution Approach 2:
The gate structure is nested around each nanosheet channel layer, with the gate dielectric layer forming a complete surrounding envelope. This nested configuration allows the dielectric layer to provide comprehensive coverage and electrical isolation without requiring additional vertical space between channels, as the gate structure integrates within the existing vertical architecture
2Reliability
If the gate dielectric layer thickness is increased to 4-5 nm for extra gate oxide layer, then the operating voltage tolerance is improved, but the manufacturing complexity increases due to precise thickness control requirements
Solution Approach 1:
The patent specifies precise thickness parameters for the gate dielectric layer (4-5 nm for extra gate oxide) and employs advanced deposition techniques such as atomic layer deposition (ALD) that offer atomic-level thickness control. By controlling the deposition parameters and cycle numbers, the manufacturing process achieves the required precision for reliable operation while managing the complexity through standardized process parameters
3Productivity
If the vertical distance between nanosheet channel layers is reduced to increase device density, then the device density is improved, but the gate dielectric layer cannot be formed with sufficient thickness
Solution Approach 1:
The gate structure extends in multiple dimensions around each nanosheet channel, providing electrical isolation and control from all directions. This multi-dimensional approach allows the gate dielectric layer to achieve sufficient effective thickness for reliability even when vertical spacing between channels is minimized, as the dielectric coverage is distributed across radial and lateral dimensions rather than relying solely on vertical distance
Data Source
AI summary
Provided is a multi-stack nanosheet structure that includes: at least a first nanosheet structure and at least a second nanosheet structure, above the substrate, separated from each other, wherein the first nanosheet structure and second nanosheet structure are adjacent to each other; a channel structure comprising a first portion on the first nanosheet structure, a second portion on the second nanosheet structure, and a third portion on the substrate between the first and second portions, wherein the first portion, the second portion and the third portion form a single continuous structure; a gate structure between the first and second portions on the third portion of the channel structure, wherein the gate structure comprises a gate dielectric layer comprising oxide; and at least a first source/drain region on the first nanosheet structure, and at least a second source/drain region on the second nanosheet structure, wherein the first source/drain region and the second source/drain region include an n-type or p-type dopant.