Multi-Stack Transistor Layout With Vertical Gate Misalignment
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Solution Overview
Problem
The challenge in forming multi-stack semiconductor devices lies in creating contact plugs on gate structures and source/drain regions without sacrificing area gain when stacking transistor structures, and existing methods either require complex processes or result in area loss.
Innovation Solution
The solution involves vertically misaligning the upper-stack transistor structure with respect to the lower-stack transistor structure, allowing the gate contact plug to directly land on the top surface of the lower gate structure without overlapping entirely, thus maintaining the same size of gate structures and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the upper-stack transistor structure is vertically aligned with the lower-stack transistor structure, then the gate contact plug cannot directly land on the lower gate structure without lateral extension, but this causes area loss and increases manufacturing complexity
Solution Approach 1:
The patent transitions from a two-dimensional planar alignment problem to a three-dimensional vertical stacking solution. By stacking the upper gate structure vertically above the lower gate structure with intentional misalignment, the gate contact plug can directly land on the lower gate structure without lateral extension, eliminating area loss while simplifying the manufacturing process.
Solution Approach 2:
The patent introduces intentional asymmetric misalignment between the upper gate structure and lower gate structure. The gate structures are positioned with a predetermined offset in the lateral direction, creating an asymmetric configuration that enables direct vertical landing of the gate contact plug on the lower gate structure, thereby avoiding the need for complex lateral extension processes.
2Reliability
If the gate contact plug is formed with lateral extension to connect to the lower gate structure, then connection is achieved, but this sacrifices area gain and increases process difficulty
Solution Approach 1:
Instead of solving the connection problem in the lateral plane through bent contact plugs, the patent moves the solution to the vertical dimension by stacking gate structures at different heights with misalignment. This allows the gate contact plug to connect reliably to the lower gate structure through a simple vertical deposition process, eliminating complex lateral extension steps.
Solution Approach 2:
The patent performs preliminary misalignment of the gate structures during the stacking process before forming the gate contact plug. By pre-positioning the upper gate structure with a lateral offset relative to the lower gate structure, the subsequent gate contact plug formation becomes a simple vertical deposition process that directly lands on the lower gate structure without requiring complex lateral extension or bending operations.
3Productivity
If the upper and lower gate structures are formed with the same size in plan view, then device density is maintained, but the gate contact plug cannot directly land on the lower gate structure without misalignment
Solution Approach 1:
The patent maintains the same planar footprint of upper and lower gate structures to preserve device density, while introducing vertical stacking with lateral misalignment. This three-dimensional configuration allows the gate contact plug to directly land on the lower gate structure without requiring sub-pixel alignment precision, as the misalignment is intentionally designed at a larger scale during the stacking process.
Data Source
AI summary
A multi-stack semiconductor device includes: a lower-stack transistor structure including a lower active region and a lower gate structure, the lower active region including a lower channel structure, and the lower gate structure surrounding the lower channel structure; an upper-stack transistor structure vertically stacked above the lower-stack transistor structure, and including an upper active region and an upper gate structure, the upper active region including an upper channel structure, and the upper gate structure surrounding the upper channel structure; and at least one gate contact plug contacting a top surface of the lower gate structure, wherein the lower gate structure and the upper gate structure have a substantially same size in a plan view, and wherein the lower gate structure is not entirely overlapped by the upper gate structure in a vertical direction.