Multistage ADC Architecture for Fast, Low-Power Crossbar Readout
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Solution Overview
Problem
Existing multistage analog-to-digital converters for crossbar-based circuits face challenges in terms of die size, power consumption, and accuracy, particularly due to the high requirements of chip area and power consumption in implementing Flash ADCs, which are impractical for crossbar-based applications.
Innovation Solution
The proposed solution involves a multistage analog-to-digital converter architecture that performs coarse and fine conversion processes using a transimpedance amplifier (TIA) and a comparator, generating both most significant bits (MSB) and least significant bits (LSB) of the digital output, with the ADC architecture optimizing die size, power consumption, and performance by sharing control circuitry and utilizing capacitive coupling for ramped comparator reference voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If Flash ADC architecture is used to achieve high conversion speed, then conversion speed is improved, but die size and power consumption increase significantly
Solution Approach 1:
The ADC conversion process is segmented into two distinct stages: a coarse conversion stage that captures the most significant bits quickly, and a fine conversion stage that refines the result with higher precision. This segmentation allows each stage to be optimized independently, achieving high overall conversion speed without requiring the excessive resources of a full Flash ADC architecture.
Solution Approach 2:
The system dynamically switches between different conversion modes and reference voltage levels during the conversion process. The comparator reference voltage is dynamically adjusted between coarse and fine conversion stages, and the circuit transitions between different operational states to optimize performance at each phase of conversion.
2Speed
If Flash ADC architecture is used to achieve high conversion speed, then conversion speed is improved, but power consumption increases significantly
Solution Approach 1:
The power consumption is segmented and managed across two conversion stages. The coarse conversion stage consumes less power and operates quickly, while the fine conversion stage consumes moderate power for the remaining refinement. This segmented approach avoids the exponential power consumption of a full Flash ADC while maintaining high conversion speed.
Solution Approach 2:
The system dynamically adjusts its operational mode and reference voltage levels to optimize power consumption at each conversion stage, switching between low-power coarse conversion and moderate-power fine conversion only when necessary, rather than maintaining high power consumption continuously.
3Measurement precision
If more comparators are used to increase measurement precision, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The measurement precision is achieved through segmentation of the conversion process into coarse and fine stages, each using a limited number of comparators. The coarse stage captures the majority of the signal range with fewer comparators, and the fine stage refines the measurement with additional comparators only where needed, avoiding the exponential increase in comparator count required by Flash ADC.
Solution Approach 2:
The system dynamically adjusts the reference voltage levels and comparator thresholds during conversion, allowing a smaller number of comparators to achieve high precision through adaptive threshold adjustment rather than relying solely on a large static array of comparators.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high accuracy, high throughput, and low-power-consumption applications with faster conversion times compared to traditional ramp ADCs, allowing for small die size and efficient in-memory computing applications that require high speed and high accuracy.
Implementation Method 1
a transimpedance amplifier (TIA) configured to produce an output voltage based on an input current
Implementation Method 2
generate, using a comparator, a first plurality of bits of the digital output by performing a coarse conversion process
Implementation Method 3
sampling an analog input voltage onto a first capacitor during a first coarse conversion period
Data Source
AI summary
In accordance with some embodiments of the present disclosure, an apparatus including a crossbar circuit is provided. The crossbar circuit may include a plurality of cross-point devices with programmable conductance, a transimpedance amplifier (TIA), and an analog-to-digital converter (ADC). The TIA is configured to produce an output voltage based on an input current corresponding to a summation of current from a first plurality of the cross-point devices. The ADC is configured to generate a digital output corresponding to a digital representation of the output voltage of the TIA. To generate the digital output, the ADC is to generate, using a comparator, a first plurality of bits (e.g., MSBs) of the digital output by performing a coarse conversion process and a second plurality of bits (e.g., LSBs) of the digital output by performing a fine conversion process on a sample-and-hold voltage produced in the coarse conversion process.