Multi-Stage ADC Circuit With Shared Reference Generation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current analog-to-digital converter (ADC) circuits for CMOS image sensors face challenges in efficiently converting analog signals to digital signals, particularly in resolving most significant bits (MSBs) and least significant bits (LSBs) in a multi-stage conversion process, which affects the precision and speed of image processing.
Innovation Solution
The proposed ADC circuit employs a multi-stage conversion method where MSBs are resolved using a SAR ADC or single-slope ADC during the first stage and LSBs are resolved using a single-slope ADC during the second stage, sharing SAR reference level generation and single-slope ramp generation between thousands of converters to enhance parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single-stage ADC conversion is used, then the conversion process is simple, but the precision and speed of image processing are insufficient
Solution Approach 1:
The ADC conversion process is divided into two stages: a first stage that resolves the most significant bits (MSBs) and a second stage that resolves the least significant bits (LSBs). This segmentation allows each stage to focus on specific bit ranges, improving overall conversion precision while managing circuit complexity through modular design
2Measurement precision
If multiple conversion stages are used to improve precision, then the accuracy increases, but the number of conversion cycles increases
Solution Approach 1:
The first stage performs preliminary conversion to resolve the MSBs before the second stage resolves the LSBs. This preliminary action establishes a foundation for the final high-precision result, allowing the system to achieve high bit resolution without requiring all conversion operations to complete sequentially in a single stage
Solution Approach 2:
The conversion process dynamically transitions between two operational modes: the first stage operates to capture the coarse MSB values, then the system dynamically switches to the second stage for fine LSB resolution. This dynamic approach optimizes the balance between conversion speed and precision by adapting the conversion depth to the specific bit range being processed
3Speed
If SAR ADC circuit is used for MSB resolution, then the conversion speed improves, but the reference level generation complexity increases
Solution Approach 1:
The SAR reference level generation circuit and the single-slope ramp generation circuit are merged into a shared resource that serves both conversion stages. This merging eliminates the need for separate reference generation circuits, reducing overall device complexity while maintaining the high conversion speed provided by the SAR ADC approach
4Productivity
If thousands of converters operate in parallel, then the productivity increases, but the power consumption increases
Solution Approach 1:
The SAR reference level generation and single-slope ramp generation circuits are designed as universal shared resources that serve all thousands of parallel converters. This multi-functionality allows the system to maintain high productivity through parallel processing while reducing total power consumption by eliminating redundant reference generation circuits in each individual converter
Data Source
Figure 1
Figure 2
Figure 3
AI summary
An ADC circuit that can resolve the most significant bits (MSBs) using a first circuit during a first stage of a multi-stage conversion and resolve the least significant bits (LSBs) using a second circuit during a second stage of the multi-stage conversion. This can be used, for example, in massively parallel applications where the reference level generation can be shared between thousands of converters.