Multi-Stage Arbiter Circuit for Low Metastability Failure

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Solution Overview

Problem

Conventional arbiter modules fail to provide metastability stability when two or more asynchronous requests occur very closely, resulting in unpredictable outputs with unpredictable delays.

Innovation Solution

An arbiter module comprising multiple stages with delay elements and logic units processes asynchronous requests to generate delayed requests, reducing metastability failure probability by calculating set delay values to avoid metastability in initial arbitration stages and subsequent stages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If MUTEX logic is used for arbitration, then the arbiter can handle asynchronous requests with wide time gaps, but it enters metastability state when two requests occur very closely

Engineering Contradiction:
Improvemetastability stabilityVSAvoidarbiter structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The arbiter is divided into multiple stages: a first arbitration stage using MUTEX logic and a second arbitration stage. This segmentation allows each stage to handle specific aspects of request arbitration, with the first stage processing requests with sufficient time gaps and the second stage handling closely occurring requests, thereby resolving the metastability issue without requiring complete redesign of the entire arbiter structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Delay elements are introduced before the second arbitration stage to preliminarily adjust the timing of requests. This preliminary action ensures that requests entering the second stage have appropriate time separation, preventing metastability conditions while maintaining the simplicity of the base MUTEX logic in the first stage.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If delay elements and multiple stages are added to reduce metastability, then reliability improves, but device complexity increases

Engineering Contradiction:
Improvemetastability failure probabilityVSAvoidnumber of arbitration stages
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Instead of implementing complex synchronization mechanisms for all possible request scenarios, the solution applies delay elements selectively in the second arbitration stage only for closely occurring requests. This partial action approach reduces metastability failure probability sufficiently without requiring N-cycle waiting periods or cascaded flip-flops for all cases, thereby limiting the increase in device complexity.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If conventional brute force synchronizer with N-cycle waiting period is used, then metastability is resolved, but synchronization latency increases to N+1 cycles

Engineering Contradiction:
Improvemetastability resolutionVSAvoidsynchronization latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The solution changes the timing parameters dynamically by using delay elements with specific delay values in the second arbitration stage. Instead of applying a fixed N-cycle waiting period to all requests, the delay elements are configured to provide just enough delay to resolve metastability for closely occurring requests, thereby reducing synchronization latency from N+1 cycles to a minimal value while maintaining reliability.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7650454B2Arbiter module providing low metastability failure probability
Publication Date: 2010.01.19 STMICROELECTRONICS PVT LTD
  • US7650454B2 patent drawing
  • US7650454B2 patent drawing
  • US7650454B2 patent drawing

AI summary

An arbiter module receives two or more closely occurring asynchronous requests and provides an output with a low metastability failure probability. The arbiter module includes a request resolving module that receives multiple asynchronous requests for providing a final output. The request resolving module includes one or more arbiter stages cascaded with each other and operatively coupled with logic units.