Multistage Biquad IIR Filtering for Parallel Audio Processing

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Solution Overview

Problem

Conventional multistage biquad filters in audio encoding and decoding processes are not efficiently parallelized due to dependency on previous output samples, leading to high instruction counts and limited processing efficiency in processors with SIMD units or multiple ALUs.

Innovation Solution

Implementing a multistage filter architecture where each biquad stage operates independently with latency between stages, allowing for parallel processing of all stages in a single sample loop using a SIMD architecture, with intermediate values buffered and retrieved as needed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional serially cascaded multistage biquad filters are used, then filtering stability is maintained, but processing speed and efficiency deteriorate due to sequential execution requirements

Engineering Contradiction:
Improveprocessing speedVSAvoidfilter architecture complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The multistage filter is segmented into independent biquad stages, each capable of operating autonomously on different input samples. This segmentation enables parallel execution of filter stages while maintaining the overall filtering function, thereby improving processing speed without requiring complex inter-stage dependencies

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The filter architecture transitions from sequential time-domain processing to parallel space-domain processing by introducing an additional dimension of independence among stages. Each stage processes different samples simultaneously, effectively adding a parallel processing dimension that resolves the speed-efficiency contradiction

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If parallel processing is implemented across all filter stages, then processing efficiency improves, but instruction count and control complexity increase

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidinstruction count
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

A single unified instruction set is designed that can universally control all biquad stages simultaneously. This universal instruction architecture allows one instruction stream to manage multiple parallel stages, improving productivity while avoiding the complexity of separate control logic for each stage

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The same biquad filter structure and instruction sequence are copied and instantiated across multiple stages. This copying approach enables parallel processing efficiency while minimizing control complexity, as each stage uses identical logic that can be executed simultaneously from a single instruction stream

Inventive Principle:
Principle #26Copying

3Measurement precision

If biquad stages operate with data dependencies, then filtering accuracy is maintained, but parallel execution capability is limited

Engineering Contradiction:
Improvefiltering accuracyVSAvoidparallel processing capability
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

Intermediate filtered values from each biquad stage are pre-calculated and stored in buffers before being combined in the final output stage. This preliminary action allows all stages to operate in parallel independently, maintaining filtering accuracy through proper buffering while maximizing parallel processing capability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Buffer memory structures serve as intermediaries between parallel biquad stages, temporarily holding intermediate results. These intermediaries enable decoupling of stages for independent parallel execution while preserving the required data flow and filtering accuracy through structured intermediate storage

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP2847860B1Multistage IIR filter and parallelized filtering of data with same
Publication Date: 2021.03.03 DOLBY LABORATORIES LICENSING CORP
  • EP2847860B1 patent drawingFigure 1~1A
  • EP2847860B1 patent drawingFigure 2~3
  • EP2847860B1 patent drawingFigure 4~5

AI summary

In some embodiments, a multistage filter whose biquad filter stages are combined with latency between the stages, a system (e.g., an audio encoder or decoder) including such a filter, and methods for multistage biquad filtering. In typical embodiments, all biquad filter stages of the filter are operable independently to perform fully parallelized processing of data. In some embodiments, the inventive multistage filter includes a buffer memory, at least two biquad filter stages, and a controller coupled and configured to assert a single stream of instructions to the filter stages. Typically, the multistage filter is configured to perform multistage filtering of a block of input samples in a single processing loop with iteration over a sample index but without iteration over a biquadratic filter stage index.