Multistage Boot Image Loading for Programmable Logic Devices
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Solution Overview
Problem
The increasing size of boot images for system-on-chip (SoC) devices leads to longer loading times, which is problematic as it delays the availability of the SoC upon power-up or reset, necessitating a method to expedite the boot process.
Innovation Solution
A method involving a hard I/O interface module and a soft bus interface module is used to configure a communication bus, allowing for the loading of boot images over a Peripheral Component Interconnect Express (PCIe) bus, with the soft bus interface module being configured to communicate between the SoC and a host device using a packet-based protocol, enabling fast and secure transfer of boot images.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the boot image size is increased to provide more functionality, then the boot image can include more instructions and configurations, but the loading time increases
Solution Approach 1:
The boot image is divided into two stages: first-stage boot loader (FSBL) and second-stage boot loader (SSBL). The FSBL is loaded from non-volatile memory to initialize the system and set up the PCIe interface, then the SSBL is loaded over the PCIe bus which provides faster transfer rates. This segmentation allows critical early initialization to use reliable slow storage while bulk loading uses high-speed bus transfer.
Solution Approach 2:
The FSBL performs preliminary actions by initializing the PCIe interface and setting up the data path before the main boot image loading. This preliminary configuration enables the subsequent high-speed PCIe transfer to occur, reducing the overall boot time by preparing the fast path in advance.
2Ease of manufacture
If a hard I/O interface module is used to configure the communication bus, then the bus can be initialized using available circuitry, but additional configuration steps are required
Solution Approach 1:
The hard I/O interface module performs self-initialization using circuitry that is available upon power-up without requiring external configuration. The module automatically configures itself to enable PCIe communication, reducing the burden on external systems and simplifying the overall boot process.
3Speed
If a soft bus interface module is configured to communicate over PCIe, then high-speed data transfer is enabled, but the module requires programming and setup
Solution Approach 1:
The soft bus interface module is pre-configured with the necessary programming instructions in the FSBL. The initialization code prepares the PCIe interface parameters, data paths, and transfer protocols before the actual boot image loading begins, enabling the high-speed transfer capability to be activated quickly without complex runtime setup.
Data Source
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AI summary
An integrated circuit (IC) (102) that includes a processor circuit can be booted by receiving, using a storage interface circuit (104) of the IC, a first boot image from a nonvolatile memory chip. The first boot image is executed on a processor circuit of the IC (102) to configure a bus interface module (116) that is designed to communicate with a host device (118) over a communication bus that links multiple devices to the IC (102). Using the bus interface module (116), a second boot image is received from the memory of the host device (118) to a memory of the IC (102). The IC (102) is booted by executing the second boot image.