Multistage Comparator Circuits for Scalable Multipath Path Selection
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Solution Overview
Problem
Existing network devices face challenges in efficiently performing multipath routing due to the high cost and difficulty in scaling up modulo arithmetic circuits for integer division and remainder determination, which are resource-intensive and difficult to implement for larger group values.
Innovation Solution
Implementing a network device with a multipath load balancer using multistage comparator-based modulo circuits that emulate integer division and remainder determination using combinational digital logic, reducing resource consumption and improving scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional modulo arithmetic circuits are used for integer division and remainder determination, then routing accuracy is maintained, but circuit area and signal timing cost increase significantly
Solution Approach 1:
The patent segments the modulo operation into multiple comparison stages. Instead of using a single complex modulo arithmetic circuit, the invention divides the calculation into several simpler comparison operations performed in sequence, where each stage compares a portion of the representative value against the group value to determine the appropriate path. This segmentation reduces the area requirement of individual circuits while maintaining routing accuracy.
Solution Approach 2:
The patent replaces traditional mechanical modulo arithmetic circuits with a comparison-based logical system. Instead of using dedicated division and remainder determination hardware, the invention uses a series of comparators that evaluate relationships between values to achieve the same routing function. This substitution reduces circuit complexity and area while preserving the accuracy needed for correct path selection.
2Adaptability or versatility
If traditional modulo arithmetic circuits are used for integer division and remainder determination, then routing functionality is achieved, but scalability to higher group values becomes difficult
Solution Approach 1:
The segmented comparison approach allows the circuit to scale to higher group values by simply adding more comparison stages rather than increasing the complexity of a single modulo circuit. Each stage handles a portion of the calculation, and the modular structure enables easy expansion to accommodate larger numbers of paths while keeping individual circuit elements simple and manageable.
Solution Approach 2:
The invention employs a dynamic, multi-stage comparison process that can adapt to different group values. Rather than a fixed complex circuit, the system uses a flexible sequence of comparisons that can be configured for various numbers of paths. This dynamic approach allows the same basic circuit structure to scale efficiently across different routing scenarios.
3Productivity
If dedicated circuits for modulo arithmetic are implemented, then packet processing efficiency is improved, but resource consumption increases
Solution Approach 1:
The patent replaces resource-intensive modulo arithmetic circuits with a more efficient comparison-based system. By using simple comparators instead of complex division and remainder circuits, the invention reduces the energy and computational resources required for each packet routing decision while maintaining the speed and efficiency needed for high-performance network processing.
Solution Approach 2:
The invention uses multiple simple, inexpensive comparison circuits instead of a single complex modulo arithmetic unit. Each comparison stage uses basic logical operations that are resource-efficient and can be quickly executed. This approach trades the use of expensive, resource-consuming dedicated modulo circuits for multiple cheaper, more efficient comparison operations that collectively achieve the same routing function with lower overall resource consumption.
Data Source
AI summary
An example apparatus for a network device is described. The apparatus can include: first logic configured to generate first codes for a packet, receive a second code that represents a number of paths through a network between the network device and a destination of the packet; first circuits, coupled to the first logic, each configured to perform a comparison of one of the first codes with the second code and provide an output depending on the comparison; and a second circuit, coupled to the first logic and the first circuits, configured to select the output of one of the first circuits as a third code that represents one of the paths.