Multistage Compiler Blocks With Metadata Feedback for ML Hardware

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Solution Overview

Problem

Existing compilers for electronic devices are static and incapable of adapting to rapidly changing environments, requiring complete redevelopment for different compilation blocks, and lack feedback for debugging, verification, and optimization, especially in complex ML hardware with multiple memory systems.

Innovation Solution

A multi-leveled compiler generates structured metadata at each stage of compilation, allowing for flexible and adaptable compiler blocks that can be swapped or optimized, providing detailed information for debugging, verification, and optimization, including memory location, precision, and data mapping decisions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a static compiler is used, then the compilation process is simple and stable, but the compiler cannot adapt to rapidly changing environments and requires complete redevelopment for different compilation blocks

Engineering Contradiction:
Improveadaptability to changing environmentsVSAvoidcompiler structure complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The compiler is divided into multiple independent compilation blocks (front-end, middle-end, back-end) that can be developed, tested, and replaced independently. Each block handles a specific phase of compilation, allowing selective replacement without affecting the entire compiler system.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The compiler architecture is designed to be dynamic and configurable, allowing different compilation blocks to be selected and switched based on specific needs. The system can adapt to different target platforms and optimization requirements by dynamically choosing appropriate compilation blocks.

Inventive Principle:
Principle #15Dynamics

2Productivity

If manual spot checking is used for memory allocation and access, then the verification process is simple, but it is time consuming and not scalable to entire networks or memory space

Engineering Contradiction:
Improveverification speedVSAvoidverification coverage
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The compiler automatically generates and maintains metadata that tracks memory allocation and access patterns throughout the entire compilation process. This self-generated information eliminates the need for manual verification while providing complete coverage of memory operations.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system incorporates feedback mechanisms where the compiler continuously monitors and records memory allocation decisions, data mapping, and access patterns. This feedback information is used to verify correctness and optimize performance automatically.

Inventive Principle:
Principle #23Feedback

3Ease of operation

If traditional black box compilation is used, then the compilation process is efficient, but there is no feedback or suggestion to the user for debugging, optimization, or correction

Engineering Contradiction:
Improveuser feedback capabilityVSAvoiddebugging time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The compiler provides comprehensive feedback through generated metadata that documents all compilation decisions, memory mappings, and optimization transformations. This feedback enables users to understand what happened during compilation and identify issues quickly.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

Metadata acts as an intermediary layer between the high-level source code and the low-level executable instructions. It provides a detailed intermediate representation that can be inspected, queried, and used for debugging without requiring direct examination of assembly code or memory operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250383850A1Multistage compiler architecture
Publication Date: 2025.12.18 MARVELL ASIA PTE LTD
  • US20250383850A1 patent drawing
  • US20250383850A1 patent drawing
  • US20250383850A1 patent drawing

AI summary

A system includes a compiler including a plurality of compiler blocks. The compiler blocks of the plurality of compiler blocks are compossible. The compiler is configured to identify one or more resources in a hardware to execute a set of low-level instructions that is generated from a high-level function in a high-level code. The compiler is further configured to determine one or more processing operations to be performed that is associated with the high-level function in the high-level code. The determining of the one or more processing operations occurs based on architecture of the hardware. The compiler is configured to compile the high-level function in the high-level code of the application into the set of low-level instructions to be executed on the hardware.