Multi-Stage DAC Resistor Rotator Layout for Compact ADCs

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Solution Overview

Problem

As the functional complexity of devices employing analog-to-digital converter (ADC) circuits increases, so does the length of digital signals, leading to greater area consumption in ADC and digital-to-analog converter (DAC) circuits, which results in reduced space for other circuitry.

Innovation Solution

The implementation of DAC circuits with multiple stages and adjusting circuits that maintain an ideal resistance level, allowing for a parallel combination of resistances, reduces the overall circuitry and area consumption compared to conventional DAC circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the length of digital signals is increased to handle more complex devices, then the functionality and precision of ADC circuits are improved, but the area consumption of DAC circuits increases

Engineering Contradiction:
Improvedigital signal lengthVSAvoidarea consumption
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The DAC circuit is divided into multiple stages, where each stage handles a portion of the digital-to-analog conversion. This segmentation allows the circuit to process longer digital signals without proportionally increasing the total area consumption, as each stage can be optimized independently and shares common circuitry.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements a nested structure where adjusting circuits are embedded within the DAC stage architecture. The adjusting circuits are integrated into the signal path between stages, allowing resistance adjustment functionality to be nested within the existing circuit framework rather than adding separate external components, thus reducing overall area consumption.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Productivity

If conventional DAC circuits are used to generate multiple DAC analog signals, then the conversion function is achieved, but the circuit complexity and area consumption increase

Engineering Contradiction:
Improvenumber of DAC analog signals generatedVSAvoidcircuitry
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Each DAC stage is designed with multi-functionality, serving both as a signal generation element and as part of the resistance adjustment mechanism. The adjusting circuits within each stage perform dual functions: fine-tuning the resistance values and enabling the stage to generate multiple analog signal levels, reducing the need for separate dedicated circuits for each function.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the adjusting circuit functionality directly into the DAC stage structure, combining what would traditionally be separate components into an integrated unit. This merging reduces the total number of discrete components and interconnections, thereby reducing circuit complexity and area consumption while maintaining the ability to generate multiple DAC analog signals.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10333544B1Digital-to-analog converter (DAC) circuits employing resistor rotator circuits configured to be included in analog-to-digital converter (ADC) circuits
Publication Date: 2019.06.25 QUALCOMM INC
  • US10333544B1 patent drawing
  • US10333544B1 patent drawing
  • US10333544B1 patent drawing

AI summary

Digital-to-analog converter (DAC) circuits employing resistor rotator circuits configured to be included in analog-to-digital converter (ADC) circuits are disclosed. In one aspect, a DAC circuit includes multiple DAC stages, each of which may be configured to generate one or more DAC analog signals corresponding to selected resistances within the DAC stage. Each DAC stage is configured to receive a corresponding top and bottom voltage. Each DAC stage is configured to generate a number of DAC analog signals based on the corresponding top voltage and the corresponding bottom voltage, as well as on the selected resistance of the DAC stage. Each DAC stage includes an adjusting circuit comprising a resistance configured to adjust a resistance of the corresponding DAC stage such that a parallel combination of the resistance of the adjusting circuit and a resistance of a next DAC stage is maintained at an ideal resistance level.