Multi-Stage FIR Equalization for Faster Storage Read Convergence
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Solution Overview
Problem
Traditional systems for reading data from magnetic storage media face significant latency and instability due to the slow adjustment of FIR equalization filter coefficients, which affects the ability to distinguish data on one track from adjacent tracks and compensate for inter-track interference.
Innovation Solution
A two-stage data processing system is employed, where the first stage optimizes initial read parameters and the second stage calculates an optimized FIR coefficient using a recursive least squares algorithm, allowing faster and more accurate equalization by applying it to subsequent stages, thereby reducing error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional single-stage FIR coefficient adjustment is used, then system complexity is low, but latency is high and stability is poor
Solution Approach 1:
The patent divides the FIR coefficient adjustment process into two distinct stages: a first data path with first FIR filters and first FIR adaptation circuitry, and a second data path with second FIR filters and second FIR adaptation circuitry. Each stage performs specific functions - the first stage provides initial stabilization while the second stage achieves faster convergence to optimal coefficients, thereby reducing overall latency without requiring complete system redesign
Solution Approach 2:
The first data path performs preliminary FIR coefficient adjustment and stabilization before the second data path takes over for fine-tuning. This preliminary action allows the system to establish a stable baseline quickly, after which the second stage can aggressively optimize coefficients with reduced risk of instability, effectively reducing the time to reach optimal performance
2Reliability
If FIR coefficient adjustment is made slowly for stability, then stability is maintained, but latency increases
Solution Approach 1:
The patent segments the coefficient adjustment process into two phases with different stability requirements. The first data path handles initial adjustment with conservative changes to ensure stability, while the second data path performs rapid coefficient optimization once the system is stabilized, achieving both stability and low latency through phased approach
Solution Approach 2:
The first FIR adaptation circuitry performs preliminary stabilization of the coefficient adjustment process before the second FIR adaptation circuitry begins rapid optimization. This preliminary stabilization ensures that when aggressive coefficient changes are made in the second stage, the system remains stable while achieving fast convergence to optimal performance
3Ease of operation
If read parameters are adjusted individually, then ease of operation is maintained, but the number of samples needed for stable output is high
Solution Approach 1:
The patent merges the adjustment of multiple read parameters (signal gain, sampling frequency, and FIR equalization filter coefficients) into an integrated two-stage process. Rather than adjusting parameters sequentially in a single stage, the system combines them across two data paths where parameters are coordinated and adjusted together, reducing the total number of samples needed while maintaining operational simplicity through unified control
Data Source
AI summary
Data read from a storage medium is first processed through a first data path including a first decoder configured to decode data output from at least one first finite impulse response (FIR) filter and first FIR adaptation circuitry configured to adjust a first FIR coefficient for the at least one first FIR filter. The data is then processed through a second data path, which includes at least one second FIR filter and second FIR adaptation circuitry configured to adjust a second FIR coefficient to reach an FIR coefficient that achieves a target minimum number of errors. The second FIR adaptation circuitry is configured to reach the FIR coefficient that achieves the target minimum number of errors faster than the first FIR adaptation circuitry. A second decoder in the second data path is configured to decode data output by the at least one second FIR filter.