Multistage Signal Frequency Conversion Circuit for Lower NCO Clock Load
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Solution Overview
Problem
Existing frequency conversion circuits in 5G communications require complex hardware and high clock frequencies, leading to increased resource costs and power consumption due to the need for complex logic operations in Numerically Controlled Oscillators (NCOs).
Innovation Solution
A multistage frequency conversion circuit is implemented, where a primary-stage frequency conversion module with a Numerically Controlled Oscillator (NCO) and subsequent-stage filters perform sampling rate conversion, reducing the clock frequency requirement for the NCO and avoiding complex logic operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-stage frequency conversion circuit is used, then the frequency conversion can be completed in one stage, but the NCO must operate on a high-multiple clock requiring complex logic operations (multiplier and adder), which increases device complexity and resource costs
Solution Approach 1:
The frequency conversion process is divided into multiple stages: a first frequency conversion stage followed by a second frequency conversion stage. This segmentation allows each NCO to operate at lower clock multiples, reducing the complexity of logic operations while maintaining overall conversion efficiency. The first NCO operates on the original signal, and the second NCO operates on the down-sampled signal, distributing the computational burden across stages.
Solution Approach 2:
Before the second frequency conversion, a down-sampling operation is performed on the output of the first NCO. This preliminary action reduces the sampling rate, allowing the second NCO to operate at a lower clock frequency with simpler logic requirements, thus reducing overall device complexity while preserving the necessary frequency conversion functionality.
2Measurement precision
If an NCO operates on a high-multiple clock to achieve accurate frequency conversion, then the frequency conversion precision is improved, but the power consumption increases due to complex logic operations
Solution Approach 1:
The frequency conversion is segmented into multiple stages with down-sampling in between. This allows precision to be maintained through multiple smaller conversion steps rather than one large conversion, while each individual NCO operates at lower power due to reduced clock multiples and simpler logic operations.
Solution Approach 2:
The down-sampling operation acts as an intermediary between two frequency conversion stages. It reduces the data rate and clock frequency requirements for the second NCO, thereby reducing power consumption while still achieving the desired overall frequency conversion precision through the combination of both stages.
3Reliability
If complex logic operations (multiplier and adder) are implemented in the NCO, then the frequency conversion accuracy is maintained, but the resource costs increase significantly
Solution Approach 1:
The complex frequency conversion task is divided into simpler sub-tasks across multiple stages. Each NCO performs a portion of the total frequency conversion with simpler logic requirements, reducing hardware resource costs while maintaining overall reliability through the cumulative effect of multiple conversion stages.
Solution Approach 2:
The down-sampling operation is performed as a preliminary action before the second frequency conversion stage. This reduces the complexity of the second NCO's logic operations by operating at a lower sampling rate, thereby reducing hardware resource costs while maintaining the necessary conversion accuracy through the combined operation of both stages.
Data Source
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AI summary
A signal frequency conversion circuit is disclosed, configured to reduce power consumption and resource costs of the signal frequency conversion circuit. Embodiments of the present invention include: a primary-stage frequency conversion module and at least one subsequent-stage frequency conversion module that is in series connection, where the primary-stage frequency conversion module includes a first filter and a numerically controlled oscillator NCO, and an output of the first filter is connected to an input of the NCO; each subsequent-stage frequency conversion module includes a second filter and a subsequent-stage frequency conversion unit, and an output of the second filter is connected to an input of the subsequent-stage frequency conversion unit; and an output of the NCO is connected to an input of a second filter in a first subsequent-stage frequency conversion module in the at least one subsequent-stage frequency conversion module in series connection. In the embodiments of the present invention, a frequency conversion requirement of an input signal is implemented by means of multistage frequency conversion, which avoids implementing the NCO on a high-multiple clock and avoids complex processing logic such as a multiplier and an adder required for implementing the NCO; therefore, power consumption and costs of the signal frequency conversion circuit are reduced.